EVB7122
27 to 930MHz Transceiver
Evaluation Board Description
3.1.5
D – word
Name
Bits
[16:0]
64d .. 131071d
Set the unlock condition of the PLL
00
01
10
11
00
01
10
11
0
2 clocks
#default
4 clocks
8 clocks
16 clocks
4 clocks
16 clocks
#default
64 clocks
256 clocks
Description
Feedback divider ratio in TX operation mode
NT
ERTM
[18:17]
Set the maximum allowed number of reference clocks
(1/f
RO
) during the phase detector output signals (UP & DOWN)
can be in-consecutive.
Set the lock condition of the PLL
LDTM
[20:19]
Set the minimum number of consecutive edges of phase
detector output cycles, without appearance of any unlock
condition.
Set mode of modulation control:
external modulation control
Modulation will be set via pin ASK/FSK.
#default
MODCTRL
[21]
1
internal modulation control
Modulation will be set via bit MODSEL (bit 19 in A-word). Nevertheless pin ASK/FSK must be
connected to either VCC or VEE.
39012 07122 02
Rev. 005
Page 12 of 24
EVB Description
June/07
MELEXIS [ Melexis Microelectronic Systems ]
