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EVB7122-915-FSK-C 参数 Datasheet PDF下载

EVB7122-915-FSK-C图片预览
型号: EVB7122-915-FSK-C
PDF下载: 下载PDF文件 查看货源
内容描述: 27〜 930MHz收发器评估板说明 [27 to 930MHz Transceiver Evaluation Board Description]
分类和应用:
文件页数/大小: 24 页 / 800 K
品牌: MELEXIS [ Melexis Microelectronic Systems ]
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EVB7122
27 to 930MHz Transceiver
Evaluation Board Description
2.1.3
Modulation Type
Modulation type
ASK / FSK
ASK
0
FSK
1
2.1.4
LNA Gain Mode
LNA gain
GAIN_LNA
high
0
low
1
2.2
Programmable User Mode Operation
The transceiver can also be used in programmable user mode. After power-up the first logic change at pin
FS0/SDEN enters into this mode. Now full programmability can be achieved via the Serial Control Interface
(SCI).
2.2.1
Serial Control Interface Description
A 3-wire (SCLK, SDTA, SDEN) Serial Control Interface (SCI) is used to program the transceiver in program-
mable user mode. At each rising edge of the SCLK signal, the logic value on the SDTA pin is written into a
24-bit shift register. The data stored in the shift register are loaded into one of the 4 appropriate latches on
the rising edge of SDEN. The control words are 24 bits lengths: 2 address bits and 22 data bits. The first two
bits (bit 23 and 22) are latch address bits. As additional leading bits are ignored, only the least significant 24
bits are serial-clocked into the shift register. The first incoming bit is the most significant bit (MSB). To
program the transceiver in multi-channel application, four 24-bit words may be sent: A-word, B-word, C-word
and D-word. If individual bits within a word have to be changed, then it is sufficient to program only the
appropriate 24-bit word. The serial data input timing and the structure of the control words are illustrated in
Fig. 2 and 3.
22
22
SDTA
SCLK
24-BIT
SHIFT REGISTER
2
A - LATCH
B - LATCH
C - LATCH
D - LATCH
22
A-word
22
22
B-word
22
00
22
C-word
SDEN
ADDR DECODER
01
10
11
22
22
D-word
Fig. 2:
SCI Block Diagram
39012 07122 02
Rev. 005
Page 6 of 24
EVB Description
June/07