MLX90251
Programmable Linear Hall Effect Sensor
Features and Benefits
Analog Signal Processing
Quad Switched Hall Plate
Chopper Stabilized Amplifier
Linear Analog Ratiometric Output Voltage
Programmable Output Quiescent Voltage (V
OQ
)
-100%V
DD
…200%V
DD
Range
Programmable Magnetic Sensitivity
Programmable Low Pass Filter
Programmable Clamping Voltage
Programmable Temperature Compensation
Melexis ID Number
Programmable Customer ID Number
Lead-free package
Application Examples
Linear Position Sensing
Rotary Position Sensing
Current Sensing
Magnetic Field Measurement
Ordering Information
Part No.
MLX90251
MLX90251
Temperature Code
E (-40° to 85°
C
C)
L (-40° to 150°C)
C
E (-40° to 85°
C
C)
Package Code
VA (4 Lead SIP)
GO (TSSOP14)
†
Option Code
0, 1, 2, 3
0, 1, 2, 3
††
Example:
MLX90251LVA-2
MLX90251EGO-2
†
Both package types (VA and GO) are lead-free (see section 15).
††
Please see section 10.4 for detailed information on the option code.
1 Functional Diagram
Supply
1
2 General Description
The MLX90251 is a CMOS Programmable,
Ratiometric Linear Hall Effect sensor IC. The
linear output voltage is proportional to the
magnetic flux density. The ratiometric output
voltage is proportional to the supply voltage. The
MLX90251 possesses active error correction
circuitry, which virtually eliminates the offset errors
normally associated with analog Hall Effect
devices. All the parameters of the MLX90251
transfer characteristic are fully programmable.
The V
OQ
(V
OUT
@ B = 0 Gauss), the Sensitivity,
the slope polarity, the Output Clamping levels, the
thermal Sensitivity drift, the internal bias point and
a low-pass filter are all programmable in end-user
applications. The MLX90251 has a very stable
thermal compensation for both the Sensitivity and
the V
OQ
over a broad temperature range. For
traceability purpose the MLX90251 will carry a
unique ID number programmed by Melexis and 24
bits of EEPROM memory are allocated for a user
programmed serial number.
OPA
OPA
Filter
OPA
4
3
2
Program
decoder
DAC
DAC
DAC
DAC
DAC
Shift Register
E E P R O M
Figure 1-1 Functional Diagram
Pin Out
V
DD
Test
V
SS
(Ground)
V
OUT
NC
Table 1: Pin out
VA
1
2
3
4
GO
2
3
5
6
1, 4, 7, 8-14
3901090251
Rev 009
DAC
Page 1 of 22
Data Sheet
Nov/06