MLX90255-BA
Linear Optical Array
Features and Benefits
128 x 1 Sensor-Element Organization (1 Not Connected, 1 dummy, 128 real, 1 dummy
and 1 Dark Pixel)
385 Dots-Per-Inch (DPI) Sensor Pitch
High Linearity and Uniformity for 256 Gray-Scale (8-Bit) Applications
High Sensitivity: 2.0V @ 10µW/cm² @ 0.7ms integration time for open cavity devices
1.7V @ 10µW/cm² @ 0.7ms integration time for glass lid devices
Special Gain Compensation for use with single LED light source
Output Referenced to Ground
Low Image Lag
Single 5V Supply
Replacement for TAOS, Inc. TSL1301 & TSL1401 and MLX90255AA
Operation to 500kHz
Applications
Linear Position Encoder
Rotary Position Encoder
Steering Torque and Angle Sensing (EPAS, ESP)
Spectrometer Applications
Bio-metrical Applications
OCR and Barcode Applications
Ordering Information
Part No.
MLX90255
MLX90255
Temperature Suffix
K (-40°C to 125°C)
K (-40°C to 125°C)
Package Code
WB (GLP-5 with glass)
UC (Die on wafer (un-sawn))
Option code
-BAM
-BAV
1. Functional Diagram
Pixel 1
Integrator Reset
Pixel 2
Pixel 132
VDD
2. Description
4
Analog OUT
3
Sample
Switching Logic
External
Load
Hold
Q1
132-Bit Shift Register
Q2
Q132
2
1
5
The MLX90255BA linear sensor array consists
of a 128 x 1 array of photodiodes, associated
charge amplifier circuitry and a pixel data-hold
function that provides simultaneous-integration
start and stop times for all pixels. The pixels
measure 200µm (H) by 66 µm (W). Operation is
simplified by internal control logic that requires
only a serial-input (SI) signal and a clock.
The sensor consists of 128 photodiodes
arranged in a linear array. Light energy falling on
a photodiode generates photocurrent, which is
integrated by the active integration circuitry
associated with that pixel. During the integration
period, a sampling capacitor connects to the
output of the integrator through an analog
switch. The amount of charge accumulated at
each pixel is directly proportional to the light
intensity and the integration time. The output
and reset of the integrators is controlled by a
132-bit shift register and reset logic. An output
cycle is initiated by clocking in a logic 1 on SI.
(continued on page 5)
Page 1 of 12
Nov/05
CLK
390109025502
Rev. 008
GND
SI
MELEXIS [ Melexis Microelectronic Systems ]
