Micrel, Inc.
KS8995MA/FQ
Contents
System Level Applications........................................................................................................................................... 8
Pin Configuration ........................................................................................................................................................ 10
Pin Description (by Number)...................................................................................................................................... 11
Pin Description (by Name) ......................................................................................................................................... 17
Introduction ................................................................................................................................................................. 23
Functional Overview: Physical Layer Transceiver .................................................................................................. 23
100BASE-TX Transmit.............................................................................................................................................. 23
100BASE-TX Receive............................................................................................................................................... 23
PLL Clock Synthesizer.............................................................................................................................................. 23
Scrambler/De-Scrambler (100BASE-TX only).......................................................................................................... 24
100BASE-FX Operation............................................................................................................................................ 24
100BASE-FX Signal Detection ................................................................................................................................. 24
100BASE-FX far End fault ........................................................................................................................................ 24
10BASE-T Transmit .................................................................................................................................................. 24
10BASE-T Receive ................................................................................................................................................... 24
Power Management.................................................................................................................................................. 24
MDI/MDI-X Auto Crossover ...................................................................................................................................... 24
Auto-Negotiation ....................................................................................................................................................... 24
Functional Overview: Switch Core ............................................................................................................................ 25
Address Look-Up ...................................................................................................................................................... 25
Learning .................................................................................................................................................................... 25
Migration ................................................................................................................................................................... 25
Aging ......................................................................................................................................................................... 25
Forwarding ................................................................................................................................................................ 25
Switching Engine ...................................................................................................................................................... 26
Media Access Controller (MAC) Operation............................................................................................................... 26
Inter-Packet Gap (IPG)
............................................................................................................................................. 26
Backoff Algorithm......................................................................................................................................................
26
Late Collision
............................................................................................................................................................ 26
Illegal Frames
........................................................................................................................................................... 26
Flow Control..............................................................................................................................................................
26
Half-Duplex Back Pressure
........................................................................................................................... 28
Broadcast Storm Protection
...................................................................................................................................... 28
MII Interface Operation ............................................................................................................................................. 29
SNI Interface Operation ............................................................................................................................................ 31
Advanced Functionality.............................................................................................................................................. 31
Spanning Tree Support............................................................................................................................................. 31
Special Tagging Mode .............................................................................................................................................. 32
IGMP Support ........................................................................................................................................................... 33
Port Mirroring Support............................................................................................................................................... 34
VLAN Support ........................................................................................................................................................... 34
Rate Limit Support .................................................................................................................................................... 35
Configuration Interface.............................................................................................................................................. 36
I
2
C Master Serial Bus Configuration
......................................................................................................................... 38
SPI Slave Serial Bus Configuration
.......................................................................................................................... 38
MII Management Interface (MIIM) ............................................................................................................................ 41
Register Description ................................................................................................................................................... 42
Global Registers ....................................................................................................................................................... 43
Register 0 (0x00): Chip ID0
...................................................................................................................................... 43
Register 1 (0x01): Chip ID1 / Start Switch
................................................................................................................ 43
Register 2 (0x02): Global Control 0
.......................................................................................................................... 43
Register 3 (0x03): Global Control 1
.......................................................................................................................... 43
Register 4 (0x04): Global Control 2
.......................................................................................................................... 44
Register 5 (0x05): Global Control 3
.......................................................................................................................... 45
Semptember 2008
5
M9999-091508
MICREL [ MICREL SEMICONDUCTOR ]
