4-BIT D
FLIP-FLOP
SY10E131
SY100E131
FEATURES
s
1100MHz min. toggle frequency
s
Extended 100E V
EE
range of –4.2V to –5.5V
s
Differential output
s
Individual and common clocks
s
Indivldual asynchronous reset
s
Paired asynchronous sets
s
Fully compatible with Industry standard 10KH,
100K ECL levels
s
Internal 75K
Ω
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E131
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E131 are high-speed quad master slave
D-type flip-flops with differential outputs designed for use
in new, high-performance ECL systems. The flip-flops may
be individually clocked by holding C
C
(Common Clock) at
a logic LOW and then using the four individual CE (Clock
Enable CE
0
–CE
3
) inputs to accomplish such clocking.
Alternatively, all four flip-flops can be clocked in common
by holding the CE inputs LOW and then using C
C
to clock
the data. In the common clock mode, the CE input acts as
a control that passes the C
C
signal to the flip-flop. Data is
clocked into the flip-flop on the rising edge of the output of
the logical OR operation between CE and C
C
(data enters
the master when both C
C
and CE are LOW and data
transfers to the slave when either CE or C
C,
or both, go
HIGH).
Asynchronous set and reset controls are provided. The
reset controls are individual and the set controls are
pairwise.
PIN CONFIGURATION
V
CCO
PIN NAMES
Pin
Q
3
Q
3
Function
Data Inputs
Clock Enables (Individual)
Resets
Common Clock
Sets (paired)
True Outputs
Inverting Outputs
V
CC
to Output
CE
2
R
3
D
2
R
2
D
0
-D
3
CE
0
-CE
3
25 24 23 22 21 20 19
R
0
-R
3
18
17
CE
3
D
3
S
12
V
EE
C
C
S
03
D
0
26
27
28
1
2
3
4
5
6
7
8
9
10 11
Q
2
Q
2
V
CC
Q
1
Q
1
Q
0
Q
0
C
C
S
03
, S
12
Q
0
-Q
3
Q
0
-Q
3
V
CCO
PLCC
TOP VIEW
J28-1
16
15
14
13
12
D
1
R
0
CE
0
CE
1
R
1
V
CCO
NC
Rev.: E
Amendment: /0
1
Issue Date: November, 1998
MICREL [ MICREL SEMICONDUCTOR ]
