ML2036CS 参数 Datasheet PDF下载

ML2036

P

DN

–INH

MODE

P

DN(1)

Inhibit

P

DN

–INH

PIN

V

I1

, Logic "0"

V

I2

, Inhibit State

Voltage, V

SS

to

V

SS

+ 0.5V

V

I3

, Logic "1"

DATA IN

SHIFT REG.

X

All 0‘s

LATI

X

Logic "1"

SINE WAVE OUTPUT

V

OUT

= 0V

(10kW to AGND)

V

OUT

goes to approximately V

OS

at the next V

OS

crossing

(See Figure 6)

V

OUT

= 0V

(10kW to AGND)

P

DN(1)

All 0‘s

Logic "1"

Note 1:

In the power down mode, the oscillator, CLK OUT 1 and CLK OUT 2, shift register, and data latch are all functional.

Table 1. Three Level P

DN

-INH Functions.

POWER DOWN MODE

0V

V

OS

INHIBIT MODE

0V

V

OS

V

X

V

f

|V

X

| =

PEAK

, FOR f

OUT

≤

CLK

256

2048

|V

X

|

≤

V

PEAK

+ V

8

π

f

OUT

+

π

PEAK

SIN

256

f

CLK

512

FOR f

OUT

> f

CLK

2048

SCK

SID

LATI

0 1 2 3 4 5 6 7 8 9 10 11 12 131415

Figure 6. Power Down and Inhibit Mode Waveforms.

9