ML2037
PIN CONFIGURATION
ML2037
16-Pin PDIP (P16)
16-Pin Wide SOIC (S16W)
D GND 1
SYNC 2
CLK OUT 3
S CLK 4
D GND 5
S DATA IN 6
S ENABLE 7
SHDN 8
16 DVCC
15 G1
14 G0
13 CLK IN
12 AVCC
11 AVCC
10 OUT
9
A GND
TOP VIEW
PIN DESCRIPTION
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1, 5
2
D GND
SYNC
Ground connection for the digital
sections of the IC.
Synchronization input. Holding this
pin low stops the sine wave output,
and resets the phase to zero.
Output of the internal high frequency
clock generator. f
CLK OUT
= �½f
CLK IN
.
Serial data clock input. Serial data is
clocked into the shift register on
falling edges of S CLK.
Serial data input for programming the
output frequency.
9
10
A GND
OUT
Ground reference for analog sections
of the IC and reference for OUT.
Sine wave output. The amplitude of
the sine wave will vary around a 2.5V
DC level.
Power supply for the analog sections of
the IC.
Input of the internal high frequency
clock generator. This pin is either
driven from an external clock input or
connected to a crystal for use with the
internal oscillator.
Output gain control. Works with G1 to
set the output amplitude to one of four
different full scale ranges.
Output gain control. Works with G0 to
set the output amplitude to one of four
different full scale ranges.
Power supply for the digital sections of
the IC.
3
4
CLK OUT
S CLK
11,12 AV
CC
13
CLK IN
6
7
S DATA IN
S ENABLE
14
Serial interface enable control. A
logic high on this pin allows data to be
entered into the latch.
15
8
SHDN
A logic high on this pin causes the
output of the generator to shut off and
places the IC in a low power standby
mode.
G0
G1
16
DV
CC
2
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
