ML2280, ML2283
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(Continued)
TYP
NOTE 3
CONDITIONS
MIN
MAX
UNITS
AC ELECTRICAL CHARACTERISTICS
f
CLK
t
ACQ
t
C
SNR
Clock Frequency
Sample-and-Hold Acquisition
Conversion Time
Signal to Noise Ratio
ML2280
Not including MUX adddressing time
V
IN
= 40kHz, 5V sine. f
CLK
= 1.333MHz
(f
SAMPLING
@
120kHz). Noise is sum of all
nonfundamental components up to 1/2
of f
SAMPLING
(Note 11)
V
IN
= 40kHz, 5V sine. f
CLK
= 1.333MHz
(f
SAMPLING
@
120kHz). THD is sum of 2,
3, 4, 5 harmonics relative to fundamental
(Note 11)
V
IN
= f
A
+ f
B
. f
A
= 40kHz, 2.5V sine.
f
B
= 39.8kHz, 2.5V Sine, f
CLK
= 1.333MHz
(f
SAMPLING
@
120kHz). IMD is (f
A
+ f
B
),
(f
A
– f
B
), (2f
A
+ f
B
), (2f
A
– f
B
), (f
A
+ 2f
B
),
(f
A
– 2f
B
) relative to fundamental (Note 11)
(Notes 4, 9)
(Note 4)
(Note 4)
C
L
= 100pF (Note 4 & 10)
Data MSB first
Data LSB first
C
L
= 10pF, R
L
= 10kW (see high impedance
test circuits) (Note 5)
C
L
= 100pF, R
L
= 2kW (Note 5)
C
IN
C
OUT
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
(Note 4)
10
1/2
8
47
1333
kHz
1/f
CLK
1/f
CLK
dB
THD
Total Harmonic Distortion
ML2280
–60
dB
IMD
Intermodulation Distortion
ML2280
–60
dB
Clock Duty Cycle
t
SET-UP
t
HOLD
t
PD1
,
t
PD0
t
1H
,
t
0H
CS
Falling Edge or Data Input
Valid to CLK Rising Edge
Data Input Valid after
CLK Rising Edge
CLK Falling Edge to Output
Data Valid
Rising Edge of
CS
to Data
Output and SARS Hi-Z
40
130
80
60
%
ns
ns
90
50
40
80
5
5
200
110
90
160
ns
ns
ns
ns
pF
pF
Capacitance of Logic Input
Capacitance of Logic Outputs
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
< GND < or V
IN
> V
CC
) the absolute value of current at that pin should be limited to
25mA or less.
0°C to 70°C and –40°C to 85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by
correlation with worst-case test conditions.
Typicals are parametric norm at 25°C.
Parameter guaranteed and 100% tested.
Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
Total unadjusted error includes offset, full-scale, linearity, multiplexer and sample-and-hold errors.
For V
IN
– • V
IN
+ the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for
analog input voltages one diode drop below ground or one diode drop greater than the V
CC
supply. Be careful, during testing at low V
CC
levels (4.5V), as high level
analog inputs (5V) can cause this input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows
50mV forward bias of either diode. This means that as long as the analog V
IN
or V
REF
does not exceed the supply voltage by more than 50mV, the output code will
be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V
DC
over temperature variations, initial
tolerance and loading.
Leakage current is measured with the clock not switching.
A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits,
the minimum time the clock is high or the minimum time the clock is low must be at least 300ns. The maximum time the clock can be high or low is 60µs.
Note 8:
Note 9:
Note 10: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for
comparator response time..
Note 11: Because of multiplexer addressing, test conditions for the ML2283 is V
IN
= 30kHz, 5V sine (f
SAMPLING
ª
89kHz)
5
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
