ML4818
CURRENT LIMIT, FAULT DETECTION AND SOFT START
Current limit is implemented when the current sensed on
I
LIM
reaches the 1V limit. At this point, the PWM cycle is
terminated. The flip flop (Figure 10) turns on the current
source to charge C
RST
and remains on for the duration of
the clock period. When C
RST
has charged to 3.4V, a soft
start reset occurs. The number of times the PWM cycle is
terminated due to over-current is “remembered” on C
RST
.
Over time, C
RST
is discharged by R
RST
providing a
measure of “forgetting” when the over-current condition
no longer occurs. This integrating fault detection is useful
in differentiation between short circuit and load surge
conditions.
Since the per cycle charge on RC
RESET
is proportional to
how early in the power cycle the over-current occurs, a
reset will occur more quickly under output short circuit
conditions (Figures 11a and 11b) than during a load surge
(Figures 11c and 11d).
When the soft start reset occurs, the output is inhibited
and the soft start capacitor is discharged. The output will
remain off until C
RST
discharges to 1.3V through R
RST
,
providing a reset delay. When the IC restarts, the error
amplifier output voltage is limited to the voltage at SOFT
START, thus limiting the duty cycle.
V+
I
SWITCH
I
1
9
C
SS
SOFT START
TERMINATE
PWM CYCLE
4
I
LIM
1V
+
–
S
V+
R1
R
SENSE
C1
Q
I2
12
R
RST
C
RST
3.4V
1.3V
R
CLOCK
RC
RESET
+
–
INHIBIT
OUTPUT
UNDER-VOLTAGE
LOCKOUT
Figure 10. Over-Current, Soft-Start, and Integrating Fault Detect Circuits.
1V
V(PIN 4)
1V
V(PIN 4)
3.4V
V(PIN 12)
3.4V
V(PIN 12)
Figure 11a, 11b. I
LIMIT
and Resulting RC
RESET
Waveforms During Short Circuit.
Figure 11c, 11d. I
LIMIT
and Resulting RC
RESET
Waveforms During Load Surge.
8
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
