ML4869
DEISGN CONSIDERATIONS
(Continued)
In applications where the ML4869 is operated at or near
the maximum output current, it is recommended to add a
10nF to 100nF ceramic or film capacitor from V
OUT
to
GND. The optimum value of the high frequency bypass
capacitor is dependent on the layout and the value of the
bulk output capacitor selected.
10µH
(SUMIDA CD5A)
ML4869
VIN
VL1
VIN
100µF
GND
SHDN
PWR GND
NC
VL2
VOUT
100µF
0.01µF
VOUT
INPUT CAPACITOR
Due to the high input current drawn at startup and
possibly during operation, it is recommended to decouple
the input with a capacitor with a value of 47µF to 100µF.
This filtering prevents the input ripple from affecting the
ML4869 control circuitry, and also improves the
efficiency by reducing the I
2
R losses during the charge
cycle of the inductor. Again, a low ESR capacitor (such as
tantalum) is recommended.
It is also recommended that low source impedance
batteries be used. Otherwise, the voltage drop across the
source impedance during high input current situations will
cause the ML4869 to fail to startup or to operate
unreliably. In general, for two cell applications the source
impedance should be less than 400mW, which means that
small alkaline cells should be avoided.
Figure 8. Design Example Schematic Diagram
DESIGN EXAMPLE
In order to design a boost converter using the ML4869,
it is necessary to define the values of a few parameters.
For this example, we have assumed that V
IN
= 3.0V to
3.6V, V
OUT
= 5.0V, and I
OUT(MAX)
= 250mA
First, it must be determined whether the ML4869 is
capable of delivering the output current. This is done
using Equation 1:
I
O U T ( 5 V )
=
0 .6 8 6
×
SHUTDOWN
To guarantee proper operation, SHDN must be pulled to
within 0.5V of GND or V
IN
to prevent excessive power
dissipation and possible oscillations. A graph of input
leakage current while in shutdown is shown in Figure 6.
−
0 .2 6 7 A
V
5V
IN ( M IN )
LAYOUT
Good layout practices will ensure the proper operation of
the ML4869. Some layout guidelines follow:
• Use adequate ground and power traces or planes
• Keep components as close as possible to the ML4869
• Use short trace lengths from the inductor to the V
L1
and
V
L2
pins and from the output capacitor to the V
OUT
pin
• Use a single point ground for the ML4869 PWR GND
pin and the input and output capacitors, and connect
the GND pin to PWR GND using a separate trace
• Separate the ground for the converter circuitry from the
ground of the load circuitry and connect at a single
point
Next, select an inductor:
As previously mentioned, it is the recommended
inductance is 10µH. Make sure that the peak current
rating of the inductor is at least 1.0A, and that the DC
resistance of the inductor is in the range of 50 to 100mW.
Finally, the value of the output capacitor is determined
using Equation 3:
C
OUT
=
44
×
10
µ
H
=
88
µ
F
5.0V
The closest standard value would be a 100µF capacitor
with an ESR rating of 100mW. If such a low ESR value
cannot be found, two 47µF capacitors in parallel could
also be used.
The complete circuit is shown in Figure 8. As mentioned
previously, the use of an input supply bypass capacitor is
strongly recommended.
7
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
