ML5800
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TRANSMITTER
Z
out
S
22
P
OUT
Output Impedance
TX buffer output power at 5.8GHz
at TXO
Matched into 50ohms, 25C and 3.3V
Matched into 50ohms, over operating
temperature and voltage range
f
DEV
BW
TX
P
SPUR
P
IMAGE
Transmit Modulation Deviation
TX Data Filter 3dB Bandwidth
TX spurious
TX Image
2/3 F
TXO
, 1/3 F
TXO
TXO pin See
Figure 6
-4
-7
22.5+j3
0
0
±512
1.4
-25
-20
3
3
kHz
MHz
dBc
dBc
Ω
dBm
INTERFACE LOGIC LEVELS
Input pins (DIN, XCEN, RXON, DATA, CLK, EN)
V
IH
V
IL
I
B
C
IN
Input high voltage
Input low voltage
Input bias current
Input capacitance
All states
1MHz test frequency
VDD*0.7
-0.4
-5
4
VDD+0.4
VDD*0.3
5
V
V
μA
pF
Output pins (AOUT_TPC, PAON, DOUT)
V
OL
V
OH
V
OL
I
o
V
OH
V
OL
AOUT open-drain voltage
PAON (PA control) output high voltage
PAON (PA control) output low voltage
PAON source/sink current
DOUT (data output) output high voltage
DOUT (data output) output low voltage
Sourcing 0.1mA
Sinking 0.1mA
I
O
=100μA, TPC Mode
Sourcing 5.0mA
Sinking 5.0mA
±5.0
VDD–0.4
0.4
±8.0
VDD-0.4
0.4
0.4
V
V
V
mA
V
V
3 WIRE SERIAL BUS TIMING
t
r
t
f
t
ck
t
ew
t
l
t
se
t
s
t
h
CLK input rise time (note 1)
CLK input fall time (note 1)
CLK period
EN pulse width
Delay from last clock rising edge to rise
of EN
EN setup time to ignore next rising CLK
DATA-to-CLK setup time
DATA-to-CLK hold time
50
200
15
15
15
15
See
Figure 5
15
15
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Serial I/O clock maximum rise and fall times are based on the minimum clock period. Longer rise and fall times
can be accommodated for slower clocks provided the rise and fall times remain less than 20% of the clock period and
all set up and hold time minimums are met with respect to the CMOS switching points (V
IL
MAX and V
IH
MIN). The
serial I/O clock rise and fall times are limited to an absolute maximum of 100ns.
DS5800-F-04
FINAL DATASHEET
JULY 2006
5
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
