ML6622
PIN DESCRIPTION
PIN#
1
NAME
ENABLE
FUNCTION
ECL input active low. When this input
is tied to LINKLED the ECL comparator
output is automatically enabled and
disabled by the Link Detect circuit.
This input can be tied to GND for
continuous enable. When the ECL
Comparator is disabled, ECL OUT–
goes low and ECL OUT+ goes high.
Link Detect Status output. LINKLED is
an open collector active low signal. It
will be active low when the input
signal applied to V
IN+
,V
IN–
exceeds
the programmed threshold level at the
THIN pin. Capable of driving a 20mA
LED indicator.
Positive Power Supply. +5 volts
Positive and Negative ECL Comparator
outputs. 1mA internal pull downs are
incorporated.
Ground connection. Used for less
noise sensitive nodes.
Positive ECL Link Detect output. Active
high when the input signal exceeds the
programmed Link Detect threshold.
1mA internal pull down current
sources.
Negative ECL Link Detect output.
Active low when the input signal
exceeds the programmed Link Detect
threshold. 1mA internal pull down
current sources.
A 2.5V reference with respect to GND.
NAME PIN #
10
THIN
FUNCTION
Threshold Input. A voltage applied to
this input pin sets the minimum
amplitude of the input signal required
to cause the link detect to activate. In
most cases this can be tied to V
REF
.
Ground connection for noise sensitive
circuits in the chip; the input amplifier,
DC restoration loop, part of the
Comparator and part of the link detect
circuit. In some system designs, it may
be advantageous to separate GND and
GNDA.
This input pin should be capacitively
coupled to the input source or to V
CC
A.
This input pin should be capacitively
coupled to the input source or to V
CC
A.
Positive power supply V
CC
for noise
sensitive circuits as mentioned in
GNDA. +5 volts.
A capacitor is tied from this pin to
V
REF
. This capacitor sets the lower
frequency rejection and helps remove
internal DC offset. This capacitor
should be 10 times larger than the
input capacitors.
A capacitor from this pin to ground
determines the Link Detect response
time. To Meet FDDI specifications this
capacitor should be 2,000pF. This
capacitor can be removed for faster
response time.
11
GNDA
2
LINKLED
12
13
14
V
IN–
V
IN+
V
CC
A
3
V
CC
4 ECL OUT+
5 ECL OUT–
6
7
GND
LINK+
15
CAP
16
8
LINK –
C
TIMER
9
V
REF
PIN CONNECTION
ML6622
16-Pin Narrow SOIC (S16N)
ENABLE
LINKLED
V
CC
ECL OUT+
ECL OUT–
GND
LINK+
LINK–
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CTIMER
CAP
V
CC
A
V
IN
+
V
IN
–
GNDA
THIN
V
REF
TOP VIEW
2
Micro Linear
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
