ML6696
FUNCTIONAL DESCRIPTION
FIBER OPTIC TRANSMITTER
The on-chip transmit PLL converts a 25MHz TTL-level
clock at CLKREF to an internal 125MHz bit clock. TXCLK
from the ML6696 clocks transmit data from the MAC into
the ML6696’s TXD<3:0> input pins upon assertion of
TXEN. Data from the TXD<3:0> inputs are 5-bit encoded
and converted from parallel to serial form at the 125MHz
clock rate. The ML6696 drives corresponding NRZI data
out from its LED driver. The LED driver at IOUT is a
current mode switch which develops the output light by
sinking current through the network LED into IOUT.
RTSET’s value determines the output current:
RTSET
=
.
125V
´
140
W
IOUT
(1)
ML6696 PHY MANAGEMENT FUNCTIONS
The ML6696 has management functions controlled by the
register locations given in Table 3 (page 12). There are
two 16-bit management registers, with several unused
locations. Register 0 is the basic control register (read/
write). Register 1 is the basic status register (read-only).
The ML6696 powers on with all management register bits
set to their default values.
The ML6696’s status and control register addresses and
functions match those described for the MII in IEEE
802.3u section 22. IEEE 802.3u specifies the management
data frame structure in section 22.2.4.4.
See IEEE 802.3u section 22.2.4 for a discussion of MII
management functions and status/control register
definitions.
INITIALIZATION INTERFACE
The ML6696 has an Initialization Interface to allow
register programming that is not supported by the MII
Management Interface. The intitialization data is loaded
at power-up and cannot be changed afterwards. The pin
EDIN selects one of three possible programming modes.
The Initialization Register bit assignment is shown in
Table 2.
EEPROM PROGRAMMING
With EDIN floating (set to a high impedance), the
ML6696 reads the 16 configuration bits from an external
serial EEPROM (93LC46 or similar) using the industry-
standard 3-wire serial I/O protocol. After power up, the
ML6696 automatically generates the address at EDIN and
the clock at ECLK to read out the 16 configuration bits.
The EEPROM generates the configuration bit stream at
EDOUT, synchronized with ECLK. Interface timing is
shown in Figure 5. It is important to note that the ML6696
expects LSBs first, whereas the 93LC46 shifts MSBs out
first. Therefore, the data pattern must be reversed before
programming it into the EEPROM.
MICROCONTROLLER PROGRAMMING
With EDIN high, the ML6696 expects the 16
configuration bits transfered directly at EDOUT,
synchronized with the first 16 clock rising edges provided
externally at ECLK after power-up. This mode is useful
with a small microcontroller; one controller can program
several ML6696 parts by selectively toggling their ECLK
pins. Interface timing is shown in Figure 6.
ML6696 HARD-WIRED DEFAULT
With EDIN low, the ML6692 responds to MII PHYAD
00000 only. "ISODIS" bit and "REPEATER" bit are 0.
where IOUT is the desired output current.
Driving TXEN low will cause the ML6696’s transmitter to
enter the idle state and output 62.5MHz idle signal.
Driving TXER high when TXEN is high causes the H
symbol (00100) to appear in the transmitted data stream.
The media access controller asserts TXER synchronously
with TXCLK’s rising edge, and the H symbol appears in
place of valid symbols in the current frame.
FIBER OPTIC RECEIVER
The data quantizer accepts data at the V
IN+/–
pins that is
above the internally-set 10mVpp threshold (typical).
The receive PLL extracts clock from the quantizer’s
output, providing jitter attenuation, and clocks the signal
through the serial-to-parallel converter. The resulting 5-bit
symbols are aligned and decoded, and appear at
RXD<3:0>. The ML6696 asserts RXDV when it’s ready to
present properly decoded receive data at RXD<3:0>. The
extracted clock appears at RXCLK. The receiver strips out
62.5MHz idle between data packets.
The receiver will assert RXER high if it detects errors in
the receive data or idle stream.
COLLISION AND CRS
COL goes high to indicate simultaneous 100BASE-FX
receive and transmit activity (a collision). CRS goes high
whenever there is either receive or transmit activity in
default mode, or only when there is receive activity in
repeater or full-duplex mode.
CLOCK INPUT
The ML6696 requires an accurate 25MHz reference at
CLKREF for internal clock generation (±50ppm, see
parameter X
NTOL
).
11
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
