July 1997
PRELIMINARY
ML6697
100BASE-TX Physical Layer with MII
GENERAL DESCRIPTION
The ML6697 implements the complete physical layer of
the Fast Ethernet 100BASE-TX standard. The ML6697
offers a single-chip per-port solution for MII-based
repeater applications. The ML6697 interfaces to the
controller through the Media Independent Interface (MII).
The ML6697 functionality includes 4B/5B encoding/
decoding, Stream Cipher scrambling/descrambling,
125MHz clock recovery/generation, receive adaptive
equalization, baseline wander correction, and MLT-3
transmitter.
FEATURES
n
Single-chip 100BASE-TX physical layer
n
Compliant to IEEE 802.3u 100BASE-TX standard
n
Supports MII-based repeater applications
n
Compliant MII (Media Indendent Interface)
n
4B/5B encoder/decoder
n
Stream Cipher scrambler/descrambler
n
125MHz clock recovery/generation
n
Baseline wander correction
n
Adaptive equalization and MLT-3 encoding/decoding
BLOCK DIAGRAM
(PLCC Package)
1
9
TXCLKIN
TXCLK
CLOCK SYNTHESIZER
3
4
5
6
7
8
TXD3
TXD2
TXD1
TXD0
TXEN
TXER
CRS
RXEN
RXCLK
RXD3
RXD2
RXD1
RXD0
RXDV
RXER
PCS TRANSMIT
STATE MACHINE
4B/5B ENCODER
SCRAMBLER
NRZ TO NRZI ENCODER
SERIALIZER
MLT-3 ENCODER
FLP/100BASE-TX
TWISTED PAIR DRIVER
TPOUTP
TPOUTN
RTSET
40
39
37
18
19
17
10
12
14
16
21
23
CLOCK AND DATA
RECOVERY
NRZI TO NRZ DECODER
PCS RECEIVE
STATE MACHINE
5B/4B DECODER
DESCRAMBLER
MII MANAGEMENT REGISTERS
AND CONTROL LOGIC
DESERIALIZER
EQUALIZER
BLW CORRECTION
MLT-3 DECODER
LOOPBACK MUX
TPINP
TPINN
CMREF
RGMSET
LINK100
45
44
46
36
43
PHYAD0
PHYAD1
PHYAD2
PHYAD3
32
24
25
29
30
31
PHYAD4
33
MDIO
MDC
1
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
