May 1997
ML6698*
100BASE-TX Physical Layer with 5-Bit Interface
GENERAL DESCRIPTION
The ML6698 is a high-speed physical layer transceiver
that provides a 5-bit (or symbol) interface to unshielded
twisted pair cable media. The ML6698 is well suited for
adapter card applications using the DEC 21143, the
Macronix MX98713, or equivalent Media Access
Controllers (MACs). The ML6698 may be used in other
100BASE-TX applications requiring the 5-bit interface as
well as FDDI-over-copper applications.
The ML6698 integrates 125MHz clock recovery/
generation, receive adaptive equalization, baseline
wander correction and MLT-3/10BASE-T transmitter.
FEATURES
s
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5-bit (or symbol) parallel interface
Compliant to IEEE 802.3u 100BASE-TX standard
Compliant to ANSI X3T12 TP-PMD (FDDI) standard
Single-jack 10BASE-T/100BASE-TX solution when used
with external 10Mbps PHY
125MHz receive clock recovery/generation
Baseline wander correction
Adaptive equalization and MLT-3 encoding/decoding
Supports full-duplex operation
*Some Packages Are End Of Life As Of August 1, 2000
BLOCK DIAGRAM
(PLCC Pin Configuration)
41
40
10BTTXINP
44
TXC
CLOCK SYTHESIZER
10BTTXINN
TPOUTP
2
3
4
5
6
TSM4
TSM3
TSM2
TSM1
TSM0
CLOCK AND DATA
RECOVERY
TPINP
EQUALIZER
BLW CORRECTION
MLT-3 DECODER
LOOPBACK MUX
DESERIALIZER
RSM2
RSM1
RSM0
CONTROL LOGIC
CMREF
RGMSET
SDO
TPINN
SERIALIZER
NRZ TO NRZI
AND
NRZI TO MLT-3
ENCODER
100BASE-TX/10BASE-T
TWISTED PAIR DRIVER
TPOUTN
RTSET
34
33
31
38
37
39
30
24
16
8
9
11
13
15
RXC
RSM4
RSM3
NRZI TO NRZ DECODER
SEL100/10
25
42
PWRDN
7
LPBK
1