Wafer-Level Burn-In
Microchip’s best-in-class field performance is the combined result of world class
manufacturing, wafer level burn-in and wafer probe quality screens.
Microchip’s Triple Test Flow is currently the most robust testing procedure for serial EEPROM devices in the
industry. It tests each cell of each die three times and also performs extensive endurance and data retention tests
to ensure quality and reliability.
Infant mortality of Microchip serial EEPROMs is among the lowest in the industry due to this extensive testing,
excellent fabrication and highly reliable memory cell design.
Traditional Burn-in
(Old Technology)
General purpose non-specific testing procedure
for random logic cells
■
Non-specific and untargeted testing
mechanism – Increases failure rates.
■
Expensive, time consuming and inefficient.
■
Introduces defect modes like bent leads
and EOS that sometimes go undetected
.
Microchip’s Triple Test and
Wafer-level Burn-in Procedure
Moving beyond traditional burn-in to wafer level burn-in with the Triple
Test Flow specifically targeted for memory cells has helped create the
industry’s most reliable memory products.
■
Extensive Testing – Every cell in every die is tested three times,
including specific endurance and data retention tests to ensure
highest quality.
■
HVST, LVHF and TVPP tests target specific defects.
■
Maverick, SBY and GBN target overall failure patterns and trends.
■
Insight into failure modes along with flexible test flow ensures
continues improvement.
Triple Test Flow
Microchip tests every cell in wafer form twice, then performs a final test after assembly.
Retention Bake
1: Wafer Probe
Full functional
tests on 100% of
die and bits;
85ºC or 125ºC
5000 erase/write
cycles on all bits
2: Wafer Probe
2nd 100% bit
test (25ºC)
full-functional
screen
3:
Assembly
& Final
Test
Main Goals – Zero Defects
■
Full verification of data sheet parameters for
functional compliance at die and package
level.
■
Removal of manufacturing defects to ensure
highest quality and reliability.
■
Screening out of functional devices that may
fail in the future.
• 250ºC up to 24 hours
• Equivalent to 100
years at 85ºC
Key Aspects:
Endurance Testing
MAVERICK
HVST
TVPP
Any die with charge loss in
any cell between the
2 probes is rejected to
prevent infant mortality
Key Aspects:
Functional Test
Verify Margins
GBN
EDIO
LVHF
SBY
Wafer Probe Quality Screens
Microchip performs additional in-house testing during wafer
probe to ensure quality and eliminate any devices that are
outside the normal distribution or might possibly fail in the
future.
High Voltage Stress Test (HVST)
HVST targets weak devices with oxide defects in RAM and logic
circuits by stressing the oxides at higher than normal voltages.
Time at Vpp (TVPP)
TVPP targets oxide defects in EEPROM cells, charge pumps
and other high-voltage circuits. Programming voltages (V
PP
) are
applied to the memory array for an extended period of time in
order to highlight any weak devices.
Low Voltage High Frequency (LVHF)
LVHF targets signal paths that are partially blocked and therefore
more resistive than normal. LVHF eliminates these devices by
requiring them to operate faster than specified and at voltages
lower than specified.
Good Die in a Bad Neighborhood (GBN) and
Edge Die Ink Out (EDIO)
Special algorithms target devices that function, but are
suspect because of their proximity to clusters of failing
devices or edge die.
Failing Die
Passing Die
Rejected by
EDIO screen
Rejected by
GBN screen
Rejected by
EDIO screen
(Concept)
What Does All of This Mean?
■
<<1 PPM Field Failures
■
Best-in-class endurance
■
Industry-leading data retention
10
Serial Memory Products
MICROCHIP [ MICROCHIP TECHNOLOGY ]
