24LC21
7.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LC21 will then
issue an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LC21 discon-
tinues transmission (Figure 7-2).
7.1
Current Address Read
7.3
Sequential Read
The 24LC21 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address
with R/W bit set to one, the 24LC21 issues an acknowl-
edge and transmits the eight bit data word. The master
will not acknowledge the transfer but does generate a
stop condition and the 24LC21 discontinues transmis-
sion (Figure 7-1).
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC21 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC21 to transmit the next sequentially
addressed 8 bit word (see Figure 7-3).
To provide sequential reads the 24LC21 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
7.2
Random Read
7.4
Noise Protection
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC21 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
The 24LC21 employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
FIGURE 7-1:
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
S
T
A
R
T
CONTROL
BYTE
S
T
O
P
DATA n
SDA LINE
S
A
C
K
N
O
A
C
K
P
BUS ACTIVITY
FIGURE 7-2:
RANDOM READ
CONTROL
BYTE
WORD
ADDRESS (n)
S
T
A
R
T
CONTROL
BYTE
S
T
O
P
S
T
BUS ACTIVITY
A
MASTER
R
T
SDA LINE
DATA n
S
A
C
K
A
C
K
S
A
C
K
N
O
A
C
K
P
BUS ACTIVITY
©
1996 Microchip Technology Inc.
DS21095F-page 9
MICROCHIP [ MICROCHIP TECHNOLOGY ]
