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24LC512T-I/SM 参数 Datasheet PDF下载

24LC512T-I/SM图片预览
型号: 24LC512T-I/SM
PDF下载: 下载PDF文件 查看货源
内容描述: 512K I2C™ CMOS串行EEPROM [512K I2C™ CMOS Serial EEPROM]
分类和应用: 存储内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 28 页 / 399 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
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24AA512/24LC512/24FC512
512K I
2
C
CMOS Serial EEPROM
Device Selection Table
Part
Number
24AA512
24LC512
24FC512
Note 1:
2:
V
CC
Range
1.7-5.5V
2.5-5.5V
1.7-5.5V
Max. Clock
Frequency
400 kHz
(1)
400 kHz
1 MHz
(2)
Temp.
Ranges
I
I, E
I
Description:
The Microchip Technology Inc. 24AA512/24LC512/
24FC512 (24XX512*) is a 64K x 8 (512 Kbit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.7V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications and data acquisi-
tion. This device also has a page write capability of up
to 128 bytes of data. This device is capable of both
random and sequential reads up to the 512K boundary.
Functional address lines allow up to eight devices on
the same bus, for up to 4 Mbit address space. This
device is available in the standard 8-pin plastic DIP,
SOIJ and DFN packages.
100 kHz for V
CC
< 2.5V
400 kHz for V
CC
< 2.5V
Features:
• Single Supply with Operation Down to 1.7V for
24AA512 and 24FC512 Devices, 2.5V for
24LC512 Devices
• Low-Power CMOS Technology:
- Active current 400 uA, typical
- Standby current 100 nA, typical
• 2-Wire Serial Interface, I
2
C
Compatible
• Cascadable for up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms max.
• Self-Timed Erase/Write Cycle
• 128-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 years
• Packages Include 8-lead PDIP, SOIJ and DFN
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E):-40°C to +125°C
Block Diagram
A0 A1 A2 WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page Latches
I/O
SCL
YDEC
SDA
V
CC
V
SS
Sense Amp.
R/W Control
Package Type
PDIP
A0
A1
A2
V
SS
1
2
3
4
24XX512
8
7
6
5
V
CC
WP
SCL
A0
A1
A2
1
24XX512
2
3
4
SOIJ
8
7
6
5
V
CC
WP
SCL
SDA
SDA V
SS
DFN
A0
A1
A2
V
SS
1
2
3
4
24XX512
8 V
CC
7 WP
6 SCL
5 SDA
* 24XX512 is used in this document as a generic part
number for the 24AA512/24LC512/24FC512 devices.
©
2008 Microchip Technology Inc.
DS21754J-page 1