93C46B
3.4
ERASE
3.5
Erase All (ERAL)
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. This cycle begins
on the rising clock edge of the last address bit.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
The Erase All (ERAL) instruction will erase the entire
memory array to the logical “1” state. The ERAL cycle
is identical to the ERASE cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the rising clock edge of the last address
bit. Clocking of the CLK pin is not necessary after the
device has entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (T
CSL
) and before the entire ERAL cycle is
complete.
FIGURE 3-2:
CS
ERASE TIMING
T
CSL
CHECK STATUS
CLK
DI
1
1
1
A
N
A
N
-1
A
N
-2
•••
A0
T
SV
T
CZ
READY
HIGH-Z
T
WC
DO
HIGH-Z
BUSY
FIGURE 3-3:
CS
ERAL TIMING
T
CSL
CHECK STATUS
CLK
DI
1
0
0
1
0
X
•••
X
T
SV
T
CZ
READY
HIGH-Z
T
EC
DO
HIGH-Z
BUSY
©
1997 Microchip Technology Inc.
Preliminary
DS21172D-page 5
MICROCHIP [ MICROCHIP TECHNOLOGY ]
