93XX46X/56X/66X/76X/86X
3.5
ERASE ALL (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the Erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93CXX’ devices where the rising edge of CLK before
the last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (T
CSL
).
V
CC
must be
≥
4.5V for proper operation of ERAL.
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
FIGURE 3-3:
ERAL TIMING FOR 93AAXX AND 93LCXX DEVICES
T
CSL
CS
Check Status
CLK
DI
High-Z
1
0
0
1
0
X
•••
X
T
SV
DO
Busy
T
EC
Vcc must be
≥
4.5V for proper operation of ERAL.
Ready
T
CZ
High-Z
FIGURE 3-4:
ERAL TIMING FOR 93CXX DEVICES
T
CSL
CS
Check Status
CLK
DI
High-Z
1
0
0
1
0
X
•••
X
T
SV
DO
Busy
T
EC
Ready
T
CZ
High-Z
DS21929D-page 12
©
2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
