MCP2515
1.5
CAN Protocol Engine
1.5.3
ERROR MANAGEMENT LOGIC
The CAN protocol engine combines several functional
blocks, shown in Figure 1-4 and described below.
The Error Management Logic (EML) is responsible for
the fault confinement of the CAN device. Its two
counters, the Receive Error Counter (REC) and the
Transmit Error Counter (TEC), are incremented and
decremented by commands from the bit stream
processor. Based on the values of the error counters,
the CAN controller is set into the states error-active,
error-passive or bus-off.
1.5.1
PROTOCOL FINITE STATE
MACHINE
The heart of the engine is the Finite State Machine
(FSM). The FSM is a sequencer that controls the
sequential data stream between the TX/RX shift
register, the CRC register and the bus line. The FSM
also controls the Error Management Logic (EML) and
the parallel data stream between the TX/RX shift
registers and the buffers. The FSM ensures that the
processes of reception, arbitration, transmission and
error-signaling are performed according to the CAN
protocol. The automatic retransmission of messages
on the bus line is also handled by the FSM.
1.5.4
BIT TIMING LOGIC
1.5.2
CYCLIC REDUNDANCY CHECK
The Cyclic Redundancy Check register generates the
Cyclic Redundancy Check (CRC) code, which is
transmitted after either the Control Field (for messages
with 0 data bytes) or the Data Field and is used to
check the CRC field of incoming messages.
The Bit Timing Logic (BTL) monitors the bus line input
and handles the bus-related bit timing according to the
CAN protocol. The BTL synchronizes on a recessive-
to-dominant bus transition at Start-of-Frame (hard syn-
chronization) and on any further recessive-to-dominant
bus line transition if the CAN controller itself does not
transmit a dominant bit (resynchronization). The BTL
also provides programmable time segments to
compensate for the propagation delay time, phase
shifts and to define the position of the sample point
within the bit time. The programming of the BTL
depends on the baud rate and external physical delay
times.
FIGURE 1-4:
RX
CAN PROTOCOL ENGINE BLOCK DIAGRAM
TX
Bit Timing Logic
SAM
Sample<2:0>
StuffReg<5:0>
Transmit
Majority
Decision
Error Counter
ErrPas
BusOff
Receive
Error Counter
TEC
REC
Transmit Logic
BusMon
Comparator
CRC<14:0>
Protocol
FSM
Comparator
Shift<14:0>
(Transmit<5:0>, Receive<7:0>)
Receive<7:0>
Transmit<7:0>
SOF
RecData<7:0>
TrmData<7:0>
Rec/Trm Addr.
Interface to Standard Buffer
DS21801D-page 6
Preliminary
©
2005 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
