PIC10F200/202/204/206
FIGURE 7-2:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC+5 PC + 6
Instruction
Fetch
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
NT0 + 1
T0
T0 + 1
T0 + 2
NT0
NT0 + 2
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
FIGURE 7-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Instruction
Fetch
T0
T0 + 1
NT0
NT0 + 1
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Power-On
Reset
Value on
All Other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
Timer0 – 8-bit Real-Time Clock/Counter
xxxx xxxx uuuu uuuu
07h
CMCON0
OPTION
CMPOUT COUTEN POL CMPT0CS CMPON CNREF CPREF CWU 1111 1111 uuuu uuuu
N/A
GPWU
—
GPPU
—
T0CS
—
T0SE
—
PSA
PS2
PS1
PS0
1111 1111 1111 1111
---- 1111 ---- 1111
(1)
N/A
TRISGPIO
I/O Control Register
Legend:
Shaded cells not used by Timer0. – = unimplemented, x = unknown, u= unchanged.
Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1.
small RC delay of 2 Tt0H) and low for at least 2 TOSC
(and a small RC delay of 2 Tt0H). Refer to the electrical
specification of the desired device.
7.1
Using Timer0 with an External
Clock (PIC10F204/206)
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock require-
ment is due to internal phase clock (TOSC) synchroniza-
tion. Also, there is a delay in the actual incrementing of
Timer0 after synchronization.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling require-
ment, the ripple counter must be taken into account.
Therefore, it is necessary for T0CKI or the comparator
output to have a period of at least 4 TOSC (and a small
RC delay of 4 Tt0H) divided by the prescaler value. The
only requirement on T0CKI or the comparator output
high and low time is that they do not violate the
minimum pulse width requirement of Tt0H. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
7.1.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of an external clock with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 7-4). Therefore, it is necessary for T0CKI or the
comparator output to be high for at least 2 TOSC (and a
DS41239D-page 34
© 2007 Microchip Technology Inc.
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