PIC12C5XX
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC12C5XX family can
be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC12C5XX uses a Harvard architecture in
which program and data are accessed on separate
buses. This improves bandwidth over traditional von
Neumann architecture where program and data are
fetched on the same bus. Separating program and
data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12-bits wide making it possible to have all
single word instructions. A 12-bit wide program
memory access bus fetches a 12-bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
execution of instructions. Consequently, all instructions
(33) execute in a single cycle (1µs @ 4MHz) except for
program branches.
The table below lists program memory (EPROM), data
memory (RAM), ROM memory, and non-volatile
(EEPROM) for each device.
Memory
Device
EPROM
Program
512 x 12
1024 x 12
512 x 12
1024 x 12
1024 x 12
512 x 12
1024 x 12
ROM
Program
RAM
Data
25
41
25
41
41
25 x 8
41 x 8
16 x 8
16 x 8
EEPROM
Data
The PIC12C5XX device contains an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the W (working) register. The
other operand is either a file register or an immediate
constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for
ALU operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC),
and Zero (Z) bits in the STATUS register. The C and
DC bits operate as a borrow and digit borrow out bit,
respectively, in subtraction. See the
SUBWF
and
ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-1.
PIC12C508
PIC12C509
PIC12C508A
PIC12C509A
PIC12CR509A
PIC12CE518
PIC12CE519
The PIC12C5XX can directly or indirectly address its
register files and data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC12C5XX has a highly
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of ‘special optimal situations’ make
programming with the PIC12C5XX simple yet efficient.
In addition, the learning curve is reduced significantly.
©
1999 Microchip Technology Inc.
DS40139E-page 9
MICROCHIP [ MICROCHIP TECHNOLOGY ]
