PIC12F609/615/617/12HV609/615
2.2.1
GENERAL PURPOSE REGISTER
FILE
FIGURE 2-3:
DATA MEMORY MAP OF
THE PIC12F609/HV609
File
Address
Indirect Addr.
(1)
TMR0
PCL
STATUS
FSR
GPIO
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
VRCON
CMCON0
CMCON1
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
ANSEL
WPU
IOC
OSCTUNE
PCON
PCLATH
INTCON
PIE1
Indirect Addr.
(1)
OPTION_REG
PCL
STATUS
FSR
TRISIO
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
The register file is organized as 64 x 8 in the
PIC12F609/615/12HV609/615, and as 128 x 8 in the
PIC12F617. Each register is accessed, either directly
or indirectly, through the File Select Register (FSR)
(see
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral features
are described in the section of that peripheral feature.
3Fh
General
Purpose
Registers
64 Bytes
Accesses 70h-7Fh
Bank 0
40h
6Fh
70h
7Fh
Accesses 70h-7Fh
Bank 1
EFh
F0h
FFh
Unimplemented data memory locations, read as ‘0’.
Note
1:
Not a physical register.
DS41302D-page 12
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
