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PIC16F627-20/P 参数 Datasheet PDF下载

PIC16F627-20/P图片预览
型号: PIC16F627-20/P
PDF下载: 下载PDF文件 查看货源
内容描述: 基于闪存的8位CMOS微控制器 [FLASH-Based 8-Bit CMOS Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 160 页 / 1657 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
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PIC16F62X
13.0
DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full V
DD
range). This memory
is not directly mapped in the register file space. Instead
it is indirectly addressed through the Special Function
Registers. There are four SFRs used to read and write
this memory. These registers are:
EECON1
EECON2 (Not a physically implemented register)
EEDATA
EEADR
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write-
time will vary with voltage and temperature as well as
from chip to chip. Please refer to AC specifications for
exact limits.
When the device is code protected, the CPU may
continue to read and write the data EEPROM memory.
The device programmer can no longer access
this memory.
Additional information on the Data EEPROM is avail-
able in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
EEDATA holds the 8-bit data for read/write, and EEADR
holds the address of the EEPROM location being
accessed. PIC16F62X devices have 128 bytes of data
EEPROM with an address range from 0h to 7Fh.
REGISTER 13-1: EEADR REGISTER (ADDRESS 9Bh)
U
bit7
R/W
EADR6
R/W
EADR5
R/W
EADR4
R/W
EADR3
R/W
EADR2
R/W
EADR1
R/W
EADR0
bit0
R = Readable bit
W = Writable bit
S = Settable bit
U = Unimplemented bit, read
as ‘0’
-n = Value at POR reset
bit 7
bit 6:0
Unimplemented Address:
Must be set to '0'
EEADR:
Specifies one of 128 locations for EEPROM Read/Write Operation
13.1
EEADR
The EEADR register can address up to a maximum of
256 bytes of data EEPROM. Only the first 128 bytes of
data EEPROM are implemented and only seven of the
eight bits in the register (EEADR<6:0>) are required.
The upper bit is address decoded. This means that
this bit should always be ’0’ to ensure that the address
is in the 128 byte memory space.
©
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 91