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PIC18F8490-I/PT 参数 Datasheet PDF下载

PIC18F8490-I/PT图片预览
型号: PIC18F8490-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚闪存微控制器与LCD驱动器和纳瓦技术 [64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology]
分类和应用: 驱动器闪存微控制器
文件页数/大小: 414 页 / 6891 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F6390/6490/8390/8490  
End-Of-Character (EOC) and cause data or framing  
errors. Therefore, to work properly, the initial character  
in the transmission must be all ‘0’s. This can be 00h  
(8 bytes) for standard RS-232 devices, or 000h  
(12 bits) for LIN bus.  
16.2.4  
AUTO-WAKE-UP ON SYNC BREAK  
CHARACTER  
During Sleep mode, all clocks to the EUSART are  
suspended. Because of this, the Baud Rate Generator  
is inactive and a proper byte reception cannot be per-  
formed. The auto-wake-up feature allows the controller  
to wake-up, due to activity on the RX1/DT1 line, while  
the EUSART is operating in Asynchronous mode.  
Oscillator start-up time must also be considered,  
especially in applications using oscillators with longer  
start-up intervals (i.e., XT or HS mode). The Sync  
Break (or Wake-up Signal) character must be of  
sufficient length and be followed by a sufficient interval  
to allow enough time for the selected oscillator to start  
and provide proper initialization of the EUSART.  
The auto-wake-up feature is enabled by setting the  
WUE bit (BAUDCON<1>). Once set, the typical receive  
sequence on RX1/DT1 is disabled and the EUSART  
remains in an Idle state, monitoring for a wake-up event  
independent of the CPU mode. A wake-up event  
consists of a high-to-low transition on the RX1/DT1  
line. (This coincides with the start of a Sync Break or a  
Wake-up Signal character for the LIN protocol.)  
16.2.4.2  
Special Considerations Using  
the WUE Bit  
The timing of WUE and RC1IF events may cause some  
confusion when it comes to determining the validity of  
received data. As noted, setting the WUE bit places the  
EUSART in an Idle mode. The wake-up event causes  
a receive interrupt by setting the RC1IF bit. The WUE  
bit is cleared after this when a rising edge is seen on  
RX1/DT1. The interrupt condition is then cleared by  
reading the RCREG1 register. Ordinarily, the data in  
RCREG1 will be dummy data and should be discarded.  
Following a wake-up event, the module generates an  
RC1IF interrupt. The interrupt is generated synchro-  
nously to the Q clocks in normal operating modes  
(Figure 16-8) and asynchronously, if the device is in  
Sleep mode (Figure 16-9). The interrupt condition is  
cleared by reading the RCREG1 register.  
The WUE bit is automatically cleared once a low-to-high  
transition is observed on the RX1 line following the  
wake-up event. At this point, the EUSART module is in  
Idle mode and returns to normal operation. This signals  
to the user that the Sync Break event is over.  
The fact that the WUE bit has been cleared (or is still  
set), and the RC1IF flag is set, should not be used as  
an indicator of the integrity of the data in RCREG1.  
Users should consider implementing a parallel method  
in firmware to verify received data integrity.  
16.2.4.1  
Special Considerations Using  
Auto-Wake-up  
To assure that no actual data is lost, check the RCIDL  
bit to verify that a receive operation is not in process. If  
a receive operation is not occurring, the WUE bit may  
then be set just prior to entering the Sleep mode.  
Since auto-wake-up functions by sensing rising edge  
transitions on RX1/DT1, information with any state  
changes before the Stop bit may signal a false  
FIGURE 16-8:  
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION  
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4  
OSC1  
WUE bit  
Bit set by user  
Auto-Cleared  
RX1/DT1 Line  
RC1IF  
Cleared due to user read of RCREG1  
Note: The EUSART remains in Idle while the WUE bit is set.  
FIGURE 16-9:  
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP  
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4  
Q1  
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4  
OSC1  
WUE bit  
Bit set by user  
Auto-Cleared  
RX1/DT1 Line  
RC1IF  
Note 1  
Cleared due to user read of RCREG1  
Sleep Ends  
SLEEPCommand Executed  
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.  
This sequence should not depend on the presence of Q clocks.  
2: The EUSART remains in Idle while the WUE bit is set.  
DS39629C-page 210  
© 2007 Microchip Technology Inc.