256Mb and 512Mb (256Mb/256Mb), P30-65nm
Introduction
Introduction
This document provides information about the Micron Flash memory (P30-65nm)
product and describes its features, operations, and specifications.
The Micron Flash memory (P30-65nm) is the latest generation of flash memory devices.
P30-65nm device will be offered in 64Mb up through 2Gb densities. This document cov-
ers specifically 256Mb and 512Mb (256Mb/256Mb) product information. Benefits in-
clude more density in less space, high-speed interface device, and support for code and
data storage. Features include high-performance synchronous-burst read mode, fast
asynchronous access times, low power, flexible security options, and three industry-
standard package choices. The P30-65nm product family is manufactured using Micron
65nm process technology.
Overview
This section provides an overview of the features and capabilities of the P30-65nm.
The P30-65nm family devices provides high performance at low voltage on a 16-bit data
bus. Individually erasable memory blocks are sized for optimum code and data storage.
Upon initial power up or return from reset, the device defaults to asynchronous page-
mode read. Configuring the Read Configuration Register enables synchronous burst-
mode reads. In synchronous burst mode, output data is synchronized with a user-sup-
plied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates technol-
ogy that enables fast factory program and erase operations. Designed for low-voltage
systems, the P30-65nm supports read operations with V
CC
at 1.8 V, and erase and pro-
gram operations with V
PP
at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming
(BEFP) provides the fastest flash array programming performance with V
PP
at 9.0 V,
which increases factory throughput. With V
PP
at 1.8 V, VCC and VPP can be tied together
for a simple, ultra low power design. In addition to voltage flexibility, a dedicated VPP
connection provides complete data protection when V
PP
≤
V
PPLK
.
A Command User Interface (CUI) is the interface between the system processor and all
internal operations of the device. An internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for block erase and program. A Status
Register indicates erase or program completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation.
Each erase operation erases one block. The Erase Suspend feature allows system soft-
ware to pause an erase cycle to read or program data in another block. Program Sus-
pend allows system software to pause programming to read other locations. Data is pro-
grammed in word increments (16 bits).
The P30-65nm protection register allows unique flash device identification that can be
used to increase system security. The individual Block Lock feature provides zero-laten-
cy block locking and unlocking. The P30-65nm device includes enhanced protection via
Password Access; this new feature allows write and/or read access protection of user-
defined blocks. In addition, the P30-65nm device also provides the full-device One-
Time Programmable (OTP) security feature.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. A 1/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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2013 Micron Technology, Inc. All rights reserved.
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