512Mb, 1Gb, 2Gb: P30-65nm
General Description
General Description
The Micron Parallel NOR Flash memory is the latest generation of Flash memory devi-
ces. Benefits include more density in less space, high-speed interface device, and sup-
port for code and data storage. Features include high-performance synchronous-burst
read mode, fast asynchronous access times, low power, flexible security options, and
three industry-standard package choices. The product family is manufactured using Mi-
cron 65nm process technology.
The NOR Flash device provides high performance at low voltage on a 16-bit data bus.
Individually erasable memory blocks are sized for optimum code and data storage.
Upon initial power up or return from reset, the device defaults to asynchronous page-
mode read. Configuring the read configuration register enables synchronous burst-
mode reads. In synchronous burst mode, output data is synchronized with a user-sup-
plied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates technol-
ogy that enables fast factory PROGRAM and ERASE operations. Designed for low-volt-
age systems, the devIce supports READ operations with V
CC
at the low voltages, and
ERASE and PROGRAM operations with V
PP
at the low voltages or V
PPH
. Buffered en-
hanced factory programming (BEFP) provides the fastest Flash array programming per-
formance with V
PP
at V
PPH
, which increases factory throughput. With V
PP
at low voltag-
es, V
CC
and V
PP
can be tied together for a simple, ultra low-power design. In addition to
voltage flexibility, a dedicated V
PP
connection provides complete data protection when
V
PP
≤
V
PPLK
.
A command user interface is the interface between the system processor and all inter-
nal operations of the device. The device automatically executes the algorithms and tim-
ings necessary for block erase and program. A status register indicates ERASE or PRO-
GRAM completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation.
Each ERASE operation erases one block. The erase suspend feature enables system soft-
ware to pause an ERASE cycle to read or program data in another block. Program sus-
pend enables system software to pause programming to read other locations. Data is
programmed in word increments (16 bits).
The protection register enables unique device identification that can be used to in-
crease system security. The individual block lock feature provides zero-latency block
locking and unlocking. The device includes enhanced protection via password access;
this new feature supports write and/or read access protection of user-defined blocks. In
addition, the device also provides the full-device OTP security feature.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2013 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
