128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
valid; the data may be partially corrupted after a pro-
gram or partially changed after an erase or lock bit
configuration. After RP# goes to logic HIGH (VIH), and
Figure 2
Device Identifier Code Memory Map
t
after RS, another command can be written.
7FFFFFh
It is important to assert RP# during system reset.
After coming out of reset, the system expects to read
from the Flash memory. During block erase, program,
or lock bit configuration mode, automated Flash memo-
ries provide status information when accessed. When
a CPU reset occurs with no Flash memory reset, proper
initialization may not occur because the Flash memory
may be providing status information instead of array
data. Micron Flash memories allow proper initializa-
tion following a system reset through the use of the RP#
input. RP# should be controlled by the same RESET#
signal that resets the system CPU.
Block 127
Reserved for Future
Implementation
7F0003h
7F0002h
Block 127 Lock Configuration
Reserved for Future
Implementation
7F0000h
7EFFFFh
(Blocks 64 through 126)
3FFFFFh
Block 63
Reserved for Future
Implementation
3F0003h
3F0002h
Block 63 Lock Configuration
READQUERY
Reserved for Future
Implementation
The READ QUERY operation produces block status
information, CFI ID string, system interface informa-
tion, device geometry information, and extended query
information.
3F0000h
3EFFFFh
(Blocks 32 through 62)
Block 31
Reserved for Future
Implementation
READIDENTIFIERCODES
1F0003h
1F0002h
The READ IDENTIFIER CODES operation produces
the manufacturer code, device code, and the block lock
configuration codes for each block (see Figure 2). The
block lock configuration codes identify locked and un-
locked blocks.
Block 31 Lock Configuration
Reserved for Future
Implementation
1F0000h
1EFFFFh
(Blocks 2 through 30)
01FFFFh
Block 1
WRITE
Reserved for Future
Implementation
Writing commands to the CEL allows reading of de-
vice data, query, identifier codes, and reading and clear-
ing of the status register. In addition, when VPEN = VPENH,
block erasure, program, and lock bit configuration can
also be performed.
010003h
010002h
Block 1 Lock Configuration
Reserved for Future
Implementation
010000h
00FFFFh
The BLOCK ERASE command requires suitable com-
mand data and an address within the block. The BYTE/
WORD PROGRAM command requires the command
and address of the location to be written to. The CLEAR
BLOCK LOCK BITS command requires the command
and any address within the device. SET BLOCK LOCK
BITS command requires the command and the block to
be locked. The CEL does not occupy an addressable
memory location. It is written to when the device is
enabled and WE# is LOW. The address and data needed
to execute a command are latched on the rising edge of
WE# or the first edge of CEx that disables the device
(see Table 2). Standard microprocessor write timings
are used.
Block 0
Reserved for Future
Implementation
000004h
000003h
000002h
000001h
000000h
Block 0 Lock Configuration
Device Code
Manufacturer Code
NOTE: When obtaining these identifier codes, A0 is not used
in either x8 or x16 modes. Data is always given on the
LOW byte in x16 mode (upper byte contains 00h).
128Mb, 64Mb, 32MbQ-FlashMemory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
9
MICRON [ MICRON TECHNOLOGY ]
