128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
GENERALDESCRIPTION
The MT28F128J3 is a nonvolatile, electrically block-
erasable (Flash), programmable memory containing
134,217,728 bits organized as 16,777,218 bytes (8 bits)
or 8,388,608 words (16 bits). This 128Mb device is orga-
nized as one hundred twenty-eight 128KB erase blocks.
The MT28F640J3 contains 67,108,864 bits organized
as 8,388,608 bytes (8 bits) or 4,194,304 words (16 bits).
This 64Mb device is organized as sixty-four 128KB erase
blocks.
can provide data protection when connected to ground.
This pin also enables program or erase lockout during
power transition.
Micron’s even-sectored Q-Flash devices offer indi-
vidual block locking that can lock and unlock a block
using the sector lock bits command sequence.
Status (STS) is a logic signal output that gives an
additional indicator of the internal state machine (ISM)
activity by providing a hardware signal of both status
and status masking. This status indicator minimizes
central processing unit (CPU) overhead and system
power consumption. In the default mode, STS acts as
an RY/BY# pin. When LOW, STS indicates that the ISM
is performing a block erase, program, or lock bit con-
figuration. When HIGH, STS indicates that the ISM is
ready for a new command.
Three chip enable (CE) pins are used for enabling and
disabling the device by activating the device’s control
logic, input buffer, decoders, and sense amplifiers.
BYTE# enables selecting x8 or x16 READs/WRITEs
to the device. BYTE# at logic LOW selects an 8-bit mode
with address A0 selecting between the low byte
and the high byte. BYTE# at logic HIGH enables 16-bit
operation.
RP# is used to reset the device. When the device is
disabled and RP# is at VCC, the standby mode is en-
abled. A reset time (tRWH) is required after RP#
switches HIGH until outputs are valid. Likewise, the
device has a wake time (tRS) from RP# HIGH until
WRITEs to the command user interface (CUI) are rec-
ognized. When RP# is at GND, it provides write protec-
tion, resets the ISM, and clears the status register.
A variant of the MT28F320J3 also supports the new
security block lock feature for additional code security.
This feature provides an OTP function for locking the
top two blocks, the bottom two blocks, or the entire
device. (Contact factory for availability.)
Similarly, the MT28F320J3 contains 33,554,432 bits
organized as 4,194,304 bytes (8 bits) or 2,097,152 words
(16 bits). This 32Mb device is organized as thirty-two
128KB erase blocks.
These three devices feature in-system block lock-
ing. They also have common flash interface (CFI) that
permits software algorithms to be used for entire fami-
lies of devices. The software is device-independent,
JEDEC ID-independent with forward and backward
compatibility.
Additionally, the scalable command set (SCS) al-
lows a single, simple software driver in all host systems
to work with all SCS-compliant Flash memory devices.
The SCS provides the fastest system/device data trans-
fer rates and minimizes the device and system-level
implementation costs.
To optimize the processor-memory interface, the
device accommodates VPEN, which is switchable during
block erase, program, or lock bit configuration, or
hardwired to VCC, depending on the application. VPEN is
treated as an input pin to enable erasing, program-
ming, and block locking. When VPEN is lower than the
VCC lockout voltage (VLKO), all program functions are
disabled. Block erase suspend mode enables the user
to stop block erase to read data from or program data to
any other blocks. Similarly, program suspend mode
enables the user to suspend programming to read data
or execute code from any unsuspended blocks.
VPEN serves as an input with 2.7V, 3.3V, or 5V for
application programming. VPEN in this Q-Flash family
128Mb, 64Mb, 32MbQ-FlashMemory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
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MICRON [ MICRON TECHNOLOGY ]
