ADVANCE
‡
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
FLASH MEMORY
FEATURES
• Single device supports asynchronous, page, and
burst operations
• Flexible dual-bank architecture
Support for true concurrent operation with zero
latency
Read bank
a
during program bank
b
and vice
versa
Read bank
a
during erase bank
b
and vice versa
• Basic configuration:
One hundred and thirty-five erasable blocks
Bank
a
(16Mb for data storage)
Bank
b
(48Mb for program storage)
• V
CC
, V
CC
Q, V
PP
voltages
1.70V (MIN), 1.90V (MAX) V
CC
, V
CC
Q
(MT28F642D18 only)
1.80V (MIN), 2.20V (MAX) V
CC
, and
2.25V (MAX) V
CC
Q (MT28F642D20 only)
1.80V (TYP) V
PP
(in-system PROGRAM/ERASE)
12V ±5% (HV) V
PP
tolerant (factory programming
compatibility)
• Random access time: 70ns @ 1.80V V
CC
1
• Burst Mode read access
MAX clock rate: 54 MHz (
t
CLK = 18.5ns)
Burst latency: 70ns @ 1.80V V
CC
and 54 MHz
t
ACLK: 15ns @ 1.80V V
CC
and 54 MHz
• Page Mode read access
1
Four-/eight-word page
Interpage read access: 70ns @ 1.80V
Intrapage read access: 30ns @ 1.80V
• Low power consumption (V
CC
= 2.20V)
Asynchronous Read < 15mA
Interpage Read < 15mA
Intrapage Read < 5mA
Continuous Burst Read < 10mA
WRITE < 55mA (MAX)
ERASE < 45mA (MAX)
Standby < 50µA (MAX)
Automatic power save (APS) feature
Deep power-down < 25µA (MAX)
• Enhanced write and erase suspend options
• Accelerated programming algorithm (APA) in-
system and in-factory
• Dual 64-bit chip protection registers for security
purposes
NOTE:
1. Data based on MT28F642D20 device.
4 Meg x 16 Async/Page/Burst Flash Memory
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02
MT28F642D18
MT28F642D20
Low Voltage, Extended Temperature
0.18µm Process Technology
PIN ASSIGNMENT
59-Ball FBGA
1
A
B
C
D
E
F
G
A11
2
A8
3
V
SS
4
V
CC
5
V
PP
6
A18
7
A6
8
A4
A12
A9
A20
CLK
RST#
A17
A5
A3
A13
A10
A21
ADV#
WE#
A19
A7
A2
A15
A14
WAIT#
A16
DQ12
WP#
A1
V
CC
Q
DQ15
DQ6
DQ4
DQ2
DQ1
CE#
A0
V
SS
DQ14
DQ13
DQ11
DQ10
DQ9
DQ0
OE#
DQ7
V
SS
Q
DQ5
V
CC
DQ3
V
CC
Q
DQ8
V
SS
Q
Top View
(Ball Down)
NOTE:
See page 7 for Ball Description Table.
See page 50 for mechanical drawing.
• Cross-compatible command support
Extended command set
Common flash interface
• PROGRAM/ERASE cycle
100,000 WRITE/ERASE cycles per block
OPTIONS
• Timing
80ns access
70ns access
• Frequency
40 MHz
54 MHz
• Boot Block Configuration
Top
Bottom
• Package
59-ball FBGA (8 x 7 ball grid)
• Operating Temperature Range
Extended (-40ºC to +85ºC)
Part Number Example:
MARKING
-80
-70
4
5
T
B
FN
ET
MT28F642D20FN-804 TET
1
©2002, Micron Technology, Inc.
‡
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.
MICRON [ MICRON TECHNOLOGY ]
