ADVANCE
‡
64Mb: x16, x32
SYNCFLASH MEMORY
SYNCFLASH
®
MEMORY
FEATURES
• PC133 SDRAM-compatible read timing
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access
• Programmable burst lengths:
1, 2 , 4, 8, or full page (read)
1, 2, 4, or 8 (write)
• LVTTL-compatible inputs and outputs
• Single 3.0V–3.6V power supply
Additional V
HH
hardware protect mode (RP#)
• Supports CAS latency of 1, 2, and 3
• Four-bank architecture supports true concurrent
operation with zero latency
Read any bank while programming or erasing
any other bank
• Deep power-down mode: 50µA (MAX)
• Cross-compatible Flash memory command set
MT28S4M16B1LC – 1 Meg x 16 x 4 banks
MT28S2M32B1LC – 512K x 32 x 4 banks
PIN ASSIGNMENT (Top View)
86-Pin TSOP
x16
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
CC
DQM0
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10
A0
A1
A2
MCL
V
CC
RP#
DNU
V
SS
Q
DNU
DNU
V
CC
Q
DNU
DNU
V
SS
Q
DNU
DNU
V
CC
Q
DNU
V
CC
x32
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
CC
DQM0
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10
A0
A1
A2
DQM2
V
CC
RP#
DQ16
V
SS
Q
DQ17
DQ18
V
CC
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
CC
Q
DQ23
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
x32
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
NC
V
SS
DQM1
DNU
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
V
CC
P
DQ31
V
CC
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
CC
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
x16
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
NC
V
SS
DQM1
A9
NC
CLK
CKE
A11
A8
A7
A6
A5
A4
A3
MCL
V
SS
V
CC
P
DNU
V
CC
Q
DNU
DNU
V
SS
Q
DNU
DNU
V
CC
Q
DNU
DNU
V
SS
Q
DNU
V
SS
OPTIONS
• Configuration
4 Meg x 16 (1 Meg x 16 x 4 banks)
2 Meg x 32 (512K x 32 x 4 banks)
• Read Timing (Cycle Time)
5.4ns @ CL3 (143 MHz)
5.4ns @ CL3 (133 MHz)
• Packages
86-pin OCPL
2
TSOP (400 mil)
90-ball FBGA
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Extended (-40ºC to +85ºC)
NOTE:
1. Contact factory for availability.
2. Off-center parting line.
Part Number Example:
MARKING
4M16
2M32
-7E
-75
NOTE:
1. The # symbol indicates signal is active LOW.
2. FBGA ball assignment is on the next page.
TG
FG
KEY TIMING PARAMETERS
None
ET
1
ACCESS
SPEED
CLOCK
TIME
SETUP
GRADE FREQUENCY CL = 2* CL = 3* TIME
-7E
-7E
-75
-75
143 MHz
133 MHz
133 MHz
100 MHz
6ns
5.4ns
5.4ns
5.4ns
1.5ns
1.5ns
1.5ns
1.5ns
HOLD
TIME
0.8ns
0.8ns
0.8ns
0.8ns
MT28S4M16B1LCTG-7E
* CL = CAS (READ) Latency
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
1
©2002, Micron Technology, Inc.
‡
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
MICRON [ MICRON TECHNOLOGY ]
