2Gb: x4, x8, x16 DDR3 SDRAM
Features
Figure 51: Mode Register ± (MR±) Definitions ................................................................................................ 135
Figure 52: READ Latency .............................................................................................................................. 130
Figure 53: Mode Register 1 (MR1) Definition ................................................................................................. 138
Figure 54: READ Latency (AL = 5, CL = 6) ....................................................................................................... 141
Figure 55: Mode Register 2 (MR2) Definition ................................................................................................. 142
Figure 56: CAS WRITE Latency ...................................................................................................................... 143
Figure 50: Mode Register 3 (MR3) Definition ................................................................................................. 145
Figure 58: MPR Block Diagram ...................................................................................................................... 146
Figure 59: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 148
Figure 6±: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 149
Figure 61: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 15±
Figure 62: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 151
Figure 63: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 153
Figure 64: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 154
Figure 65: Example: tFAW ............................................................................................................................. 155
Figure 66: READ Latency .............................................................................................................................. 156
Figure 60: Consecutive READ Bursts (BL8) .................................................................................................... 158
Figure 68: Consecutive READ Bursts (BC4) .................................................................................................... 158
Figure 69: Nonconsecutive READ Bursts ....................................................................................................... 159
Figure 0±: READ (BL8) to WRITE (BL8) .......................................................................................................... 159
Figure 01: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 16±
Figure 02: READ to PRECHARGE (BL8) .......................................................................................................... 16±
Figure 03: READ to PRECHARGE (BC4) ......................................................................................................... 161
Figure 04: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 161
Figure 05: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 161
Figure 06: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 163
Figure 00: Data Strobe Timing – READs ......................................................................................................... 164
Figure 08: Method for Calculating tLZ and tHZ ............................................................................................... 165
Figure 09: tRPRE Timing ............................................................................................................................... 165
Figure 8±: tRPST Timing ............................................................................................................................... 166
Figure 81: tWPRE Timing .............................................................................................................................. 168
Figure 82: tWPST Timing .............................................................................................................................. 168
Figure 83: WRITE Burst ................................................................................................................................ 169
Figure 84: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 10±
Figure 85: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 10±
Figure 86: Nonconsecutive WRITE to WRITE ................................................................................................. 101
Figure 80: WRITE (BL8) to READ (BL8) .......................................................................................................... 101
Figure 88: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 102
Figure 89: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 103
Figure 9±: WRITE (BL8) to PRECHARGE ........................................................................................................ 104
Figure 91: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 104
Figure 92: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 105
Figure 93: Data Input Timing ........................................................................................................................ 106
Figure 94: Self Refresh Entry/Exit Timing ...................................................................................................... 108
Figure 95: Active Power-Down Entry and Exit ................................................................................................ 182
Figure 96: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 183
Figure 90: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 183
Figure 98: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 184
Figure 99: Power-Down Entry After WRITE .................................................................................................... 184
Figure 1±±: Power-Down Entry After WRITE with Auto Precharge (WRAP) ...................................................... 185
Figure 1±1: REFRESH to Power-Down Entry .................................................................................................. 185
Figure 1±2: ACTIVATE to Power-Down Entry ................................................................................................. 186
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
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