欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT42L 参数 Datasheet PDF下载

MT42L图片预览
型号: MT42L
PDF下载: 下载PDF文件 查看货源
内容描述: [Ultra low-voltage core and I/O power supplies – VDD2 = 1.14–1.30V – VDDCA/VDDQ = 1.14–]
分类和应用:
文件页数/大小: 172 页 / 2069 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT42L的Datasheet PDF文件第2页浏览型号MT42L的Datasheet PDF文件第3页浏览型号MT42L的Datasheet PDF文件第4页浏览型号MT42L的Datasheet PDF文件第5页浏览型号MT42L的Datasheet PDF文件第6页浏览型号MT42L的Datasheet PDF文件第7页浏览型号MT42L的Datasheet PDF文件第8页浏览型号MT42L的Datasheet PDF文件第9页  
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Mobile LPDDR2 SDRAM
MT42L256M16D1, MT42L128M32D1, MT42L256M32D2,
MT42L128M64D2, MT42L512M32D4, MT42L192M64D3,
MT42L256M64D4, MT42L384M32D3
Features
• Ultra low-voltage core and I/O power supplies
– V
DD2
= 1.14–1.30V
– V
DDCA
/V
DDQ
= 1.14–1.30V
– V
DD1
= 1.70–1.95V
• Clock frequency range
– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)
• Four-bit prefetch DDR architecture
• Eight internal banks for concurrent operation
• Multiplexed, double data rate, command/address
inputs; commands entered on every CK edge
• Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
• Programmable READ and WRITE latencies (RL/WL)
• Programmable burst lengths: 4, 8, or 16
• Per-bank refresh for concurrent operation
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock stop capability
• RoHS-compliant, “green” packaging
Table 1: Key Timing Parameters
Speed Clock Rate Data Rate
Grade
(MHz)
(Mb/s/pin)
-18
-25
-3
533
400
333
1066
800
667
RL
8
6
5
WL
4
3
2
t
RCD/
t
RP
1
Options
Marking
Typical
Typical
Typical
• V
DD2
: 1.2V
L
• Configuration
– 32 Meg x 16 x 8 banks x 1 die
256M16
– 16 Meg x 32 x 8 banks x 1 die
128M32
– 16 Meg x 32 x 8 banks x 2 die
256M32
– 1 (16 Meg x 32 x 8 banks) + 2 (32
384M32
Meg x 16 x 8 banks)
– 32 Meg x 16 x 8 banks x 4 die
512M32
– 16 Meg x 32 x 8 banks x 2 die
128M64
– 16 Meg x 32 x 8 banks x 3 die
192M64
– 16 Meg x 32 x 8 banks x 4 die
256M64
• Device type
– LPDDR2-S4, 1 die in package
D1
– LPDDR2-S4, 2 die in package
D2
– LPDDR2-S4, 3 die in package
D3
– LPDDR2-S4, 4 die in package
D4
• FBGA “green” package
– 134-ball FBGA (10mm x
GU, GV
11.5mm)
– 168-ball FBGA (12mm x 12mm)
LF, LG
– 216-ball FBGA (12mm x 12mm) LH, LK, LL, LM,
LP
– 220-ball FBGA (14mm x 14mm)
LD, MP
– 240-ball FBGA (14mm x 14mm)
MC
– 253-ball FBGA (11mm x 11mm)
EU, EV
• Timing – cycle time
– 1.875ns @ RL = 8
-18
– 2.5ns @ RL = 6
-25
– 3.0ns @ RL = 5
-3
• Operating temperature range
– From –30°C to +85°C
WT
– From –40°C to +105°C
AT
• Revision
:A
Note:
1. For Fast
t
RCD/
t
RP, contact factory.
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.