256Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications – I
DD
Electrical Specifications – I
DD
Table 2:
I
DD
Specifications and Conditions (x4, x8, x16: -5B, -6, -6T) – Die Revision K
V
DDQ
= 2.6V ±0.1V, V
DD
= 2.6V ±0.1V (-5B); V
DDQ
= 2.5V ±0.2V, V
DD
= 2.5V ±0.2V (-6, -6T);
0°C
T
A
70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages 35–40; See also Table 1 on page 18
Parameter/Condition
Operating one-bank precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per
clock cycle; Address and control inputs changing once every
two clock cycles
Operating one-bank active-read-precharge current:
Burst = 4;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); I
OUT
= 0mA;
Address and control inputs changing once per clock cycle
Precharge power-down standby current:
All banks idle;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
Idle standby current:
CS# = HIGH; All banks are idle;
t
CK =
t
CK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle; V
IN
= V
REF
for DQ, DQS,
and DM
Active power-down standby current:
One bank active;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
Active standby current:
CS# = HIGH; CKE = HIGH; One bank
active;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
Operating burst read current:
Burst = 2;
Continuous
burst reads; One bank active; Address and control inputs
changing once per clock cycle;
t
CK =
t
CK (MIN);
I
OUT
= 0mA
Operating burst write current:
Burst = 2; Continuous burst
writes; One bank active; Address and control inputs changing
once per clock cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
t
REFC =
t
RFC (MIN)
Auto refresh burst current:
t
REFC =7.8µs
Self refresh current:
CKE
0.2V
Standard
Low power (L)
Operating bank interleave read current:
Four-bank
interleaving READs (burst = 4) with auto precharge;
t
RC = minimum
t
RC allowed;
t
CK =
t
CK (MIN); Address and
control inputs change only during ACTIVE, READ, or WRITE
commands
Symbol
-5B
100
-6/6T
90
Units
mA
Notes
I
DD0
I
DD1
120
115
mA
I
DD2P
I
DD2F
4
50
4
50
mA
mA
I
DD3P
35
60
30
55
mA
mA
I
DD3N
I
DD4R
180
160
mA
I
DD4W
180
160
mA
I
DD5
I
DD5A
I
DD6
I
DD6A
I
DD7
160
6
4
2
290
160
6
4
2
270
mA
mA
mA
mA
mA
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
256Mb_DDR_x4x8x16_D2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN
16
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