256Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 5:
Clock Input Operating Conditions
Notes: 1–5, 16, 17, and 31 apply to the entire table; Notes appear on page 35;
0°C
T
A
70°C; V
DDQ
= 2.5V ±0.2V, V
DD
= 2.5V ±0.2V (V
DDQ
= 2.6V ±0.1V, V
DD
= 2.6V ±0.1V for -5B)
Parameter/Condition
Clock input mid-point voltage: CK and CK#
Clock input voltage level: CK and CK#
Clock input differential voltage: CK and CK#
Clock input differential voltage: CK and CK#
Clock input crossing point voltage: CK and CK#
Symbol
V
MP(DC)
V
IN(DC)
V
ID(DC)
V
ID(AC)
V
IX(AC)
Min
1.15
–0.3
0.36
0.7
0.5 × V
DDQ
- 0.2
Max
1.35
V
DDQ
+ 0.3
V
DDQ
+ 0.6
V
DDQ
+ 0.6
0.5 × V
DDQ
+ 0.2
Units
V
V
V
V
V
Notes
Figure 2:
2.80V
SSTL_2 Clock Input
Maximum
clock
level
1
CK#
1.45V
1.25V
1.05V
X
3
V
MP(DC)2
V
IX(AC)
X
V
ID(DC)4
V
ID(AC)5
CK
–0.30V
Minimum
clock
level
1
Notes:
1.
2.
3.
4.
5.
6.
7.
CK or CK# may not be more positive than
V
DDQ
+ 0.3V or more negative than V
SS
- 0.3V.
This provides a minimum of 1.15V to a maximum of 1.35V and is always half of
V
DDQ
.
CK and CK# must cross in this region.
CK and CK# must meet at least V
ID(DC),min
when static and is centered around V
MP(DC)
.
CK and CK# must have a minimum 700mV peak-to-peak swing.
For AC operation, all DC clock requirements must also be satisfied.
Numbers in diagram reflect nominal values for all devices other than -5B.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN
21
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©2003 Micron Technology, Inc. All rights reserved.
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