256Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 12:
Electrical Characteristics and Recommended AC Operating Conditions (-6T)
Notes: 1–6, 16–18, and 34 apply to the entire table; Notes appear on page 35;
0°C
T
A
70°C; V
DDQ
= 2.5V ±0.2V, V
DD
= 2.5V ±0.2V
AC Characteristics
Parameter
Access window of DQ from CK/CK#
CK high-level width
Clock cycle time
Symbol
t
AC
t
CH
-6T (TSOP)
Min
–0.70
0.45
6
7.5
0.45
0.45
1.75
–0.6
0.35
0.35
–
0.75
0.45
0.2
0.2
t
CH,
t
CL
–
0.75
0.8
2.2
0.75
0.8
–0.7
12
t
HP -
t
QHS
–
15
42
60
15
–
–
72
15
0.9
0.4
12
0
0.25
0
0.4
Max
0.70
0.55
13
13
0.55
–
–
0.6
–
–
0.45
1.25
–
–
–
–
0.7
–
–
–
–
–
–
–
–
0.55
–
70,000
–
–
70.3
7.8
–
–
1.1
0.6
–
–
–
–
0.6
Units
ns
t
CK
Notes
CL = 2.5
CL = 2
t
CK
CK low-level width
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS–DQ skew, DQS to last DQ valid, per group, per access
WRITE command to first DQS latching transition
DQ and DM input setup time relative to DQS
DQS falling edge from CK rising - hold time
DQS falling edge to CK rising - setup time
Half-clock period
Data-out High-Z window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input pulse width (for each input)
Address and control input setup time (fast slew rate)
Address and control input setup time (slow slew rate)
Data-out Low-Z window from CK/CK#
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE-to-READ with auto precharge command
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE/AUTO REFRESH command period
ACTIVE-to-READ or WRITE delay
REFRESH-to-REFRESH command interval
Average periodic refresh interval
AUTO REFRESH command period
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank
a
to ACTIVE bank
b
command
Terminating voltage delay to V
SS
DQS write preamble
DQS write preamble setup time
DQS write postamble
(2.5)
(2)
t
CL
t
DH
t
DIPW
t
DQSCK
t
DQSH
t
DQSL
t
DQSQ
t
DQSS
t
DS
t
DSH
t
DSS
t
HP
t
CK
t
ns
ns
t
CK
ns
ns
ns
t
CK
t
CK
ns
t
CK
ns
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
t
CK
t
CK
ns
ns
t
CK
ns
t
CK
HZ
t
IH
F
t
IH
S
t
IPW
t
IS
t
IS
t
F
S
t
LZ
MRD
t
QH
t
QHS
t
RAP
t
RAS
t
RC
t
RCD
t
REFC
t
REFI
t
RFC
t
RP
t
RPRE
t
RPST
t
RRD
t
VTD
t
WPRE
t
WPRES
t
WPST
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DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN
27
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