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MT46V32M8FJ-75Z 参数 Datasheet PDF下载

MT46V32M8FJ-75Z图片预览
型号: MT46V32M8FJ-75Z
PDF下载: 下载PDF文件 查看货源
内容描述: 双倍数据速率DDR SDRAM [DOUBLE DATA RATE DDR SDRAM]
分类和应用: 内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 8 页 / 152 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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PRELIMINARY
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
• 167 MHz Clock, 333 Mb/s/p data rate
• V
DD
= +2.5V ±0.2V, V
DD
Q = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two - one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two - one per byte)
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
• FBGA package available
• 2.5V I/O (SSTL_2 compatible)
t
RAS lockout (
t
RAP =
t
RCD)
• Backwards compatible with DDR200 and DDR266
MT46V64M4 – 16 Meg x 4 x 4 banks
MT46V32M8 – 8 Meg x 8 x 4 banks
MT46V16M16 – 4 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:
DDR333 COMPATIBILITY
DDR333 meets or surpasses all DDR266 timing re-
quirements thus assuring full backwards compatibility
with current DDR designs. In addition, these devices
support concurrent auto-precharge and
t
RAS lockout
for improved timing performance. The 256Mb,
DDR333 device will support an (
t
REFI) average peri-
odic refresh interval of 7.8us.
The standard 66-pin TSOP package is offered for
point-to-point applications where the FBGA package
is intended for the multi-drop systems.
The Micron 256Mb data sheet provides full specifi-
cations and functionality unless specified herein.
CONFIGURATION
Architecture
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
64 Meg x 4
32 Meg x 8
16 Meg x 16
16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
2K (A0–A9, A11)
8K
8K (A0–A12)
4 (BA0, BA1)
1K (A0–A9)
8K
8K (A0–A12)
4 (BA0, BA1)
512 (A0– A8)
OPTIONS
PART NUMBER
64M4
32M8
16M16
TG
FJ
-6
-6T
-75Z
none
• Configuration
64 Meg x 4 (16 Meg x 4 x 4 banks)
32 Meg x 8 (8 Meg x 8 x 4 banks)
16 Meg x 16 (4 Meg x 16 x 4 banks)
• Plastic Package
66-Pin TSOP (OCPL)
60-Ball FBGA (16x9mm)
• Timing - Cycle Time
6ns @ CL = 2.5 (DDR333B–FBGA)
1
6ns @ CL = 2.5 (DDR333B–TSOP)
1
7.5ns @ CL = 2 (DDR266A)
2
• Self Refresh
Standard
KEY TIMING PARAMETERS
3
SPEED
GRADE
-6
-6T
-75Z
NOTE:
CLOCK RATE
CL = 2
1
DATA-OUT ACCESS DQS-DQ
1
CL = 2.5
WINDOW
2
WINDOW
2.15ns
2.0ns
2.5ns
±0.70ns
±0.75ns
±0.75ns
SKEW
+0.35ns
+0.45ns
+0.50ns
133 MHz
133 MHz
133 MHz
167 MHz
167 MHz
133 MHz
1. CL = CAS (Read) Latency
2. With a 50/50 clock duty cycle and a minimum clock
rate @ CL = 2 ( -75Z) and CL = 2.5 (-6, -6T).
3. -75, -8 are also available; see base data sheet.
NOTE:
1. Supports PC2700 modules with 2.5-3-3 timing
2. Supports PC2100 modules with 2-3-3 timing
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION AND DATA SHEET SPECIFICATIONS.