ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
the sequential and the interleaved burst types.
Reserved states should not be usedꢀ as unknown
operation or incompatibility with future versions may
result.
figuration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.
When a READ or WRITE command is issuedꢀ a block
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
blockꢀ meaning that the burst will wrap within the block
if a boundary is reached. The block is uniquely se-
lected by A1-Ai when the burst length is set to twoꢀ by
A2-Ai when the burst length is set to four and by A3-Ai
when the burst length is set to eight (where Ai is the
most significant column address bit for a given con-
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst lengthꢀ the burst type and the start-
ing column addressꢀ as shown in Table 1.
BA1
A8
A6 A5 A4
A1
A0
Address Bus
BA0 A12 A11 A10
A9
A7
A3 A2
Table 1
Burst Definition
14 13
11
9
8
6
5
4
1
12
10
7
3
2
0
Mode Register (Mx)
0* 0*
Operating Mode
CAS Latency BT Burst Length
Burst
StartingColumn
Address
OrderofAccessesWithinaBurst
Length
Type=Sequential
Type=Interleaved
* M14 and M13 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
A0
0
1
Burst Length
0-1
1-0
0-1
1-0
M2 M1 M0
M3 = 0
Reserved
2
M3 = 1
Reserved
2
2
4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A1 A0
4
4
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
8
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A2 A1 A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Burst Type
Sequential
Interleaved
M3
0
1
8
CAS Latency
Reserved
Reserved
2
M6 M5 M4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
2.5
NOTE: 1. For a burst length of two, A1-Ai select the two-
data-element block; A0 selects the first access
within the block.
Reserved
2. For a burst length of four, A2-Ai select the four-
data-element block; A0-A1 select the first access
within the block.
3. For a burst length of eight, A3-Ai select the eight-
data-element block; A0-A2 select the first access
within the block.
4. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
M12 M11 M10 M9 M8 M7
M6-M0
Valid
Valid
-
Operating Mode
Normal Operation
0
0
-
0
0
-
0
0
-
0
0
-
0
1
-
0
0
-
Normal Operation/Reset DLL
All other states reserved
Figure 1
Mode Register Definition
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001,MicronTechnology,Inc.
10
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