256Mb: x4, x8, x16 DDR SDRAM
Features
Table 2:
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
Addressing
64 Meg x 4
16 Meg x 4 x 4 banks
8K
8K (A[12:0])
4 (BA[1:0])
2K (A[9:0], A11)
32 Meg x 8
8 Meg x 8 x 4 banks
8K
8K (A[12:0])
4 (BA[1:0])
1K (A[9:0])
16 Meg x 16
4 Meg x 16 x 4 banks
8K
8K (A[12:0])
4 (BA[1:0])
512 (A[8:0])
Table 3:
Marking
-5B
1
-6
-6T
-75E
-75Z
-75
Speed Grade Compatibility
PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600(2-2-2)
Yes
–
–
–
–
–
-5B
Notes:
Yes
Yes
Yes
–
–
–
-6/-6T
Yes
Yes
Yes
Yes
–
–
-75E
Yes
Yes
Yes
Yes
Yes
–
-75Z
Yes
Yes
Yes
Yes
Yes
Yes
-75
Yes
Yes
Yes
Yes
Yes
Yes
-75
1. The -5B device is backward compatible with all slower speed grades. The voltage range of
-5B device operating at slower speed grades is V
DD
= V
DDQ
= 2.5V ± 0.2V.
Figure 1:
256Mb DDR SDRAM Part Numbers
Example Part Number: MT46V16M16P-6T:M
-
MT46V
Configuration
Package
Speed
:
Sp.
Op. Temp. Revision
Configuration
64 Meg x 4
32 Meg x 8
16 Meg x 16
Package
400-mil TSOP
400-mil TSOP (Pb-free)
8mm x 12.5mm FBGA
8mm x 12.5mm FBGA (Pb-free)
TG
P
CV
CY
IT
Revision
64M4
32M8
16M16
:K
x4, x8, x16
:M
x4, x8, x16
Operating Temp.
Commercial
Industrial
Special Options
Standard
L
Low power
-5B
-6
-6T
Speed Grade
tCK = 5ns, CL = 3
tCK = 6ns, CL = 2.5
tCK = 6ns, CL = 2.5
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
256Mb_DDR_x4x8x16_D1.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN
2
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©2003 Micron Technology, Inc. All rights reserved.