PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 3: Functional Block Diagram 128 Meg x8
CKE
CK#
CK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
COMMAND
DECODE
MODE REGISTERS
REFRESH 14
COUNTER
16
14
ROW-
ADDRESS
MUX
14
BANK0
ROW-
ADDRESS
16,384
LATCH
&
DECODER
BANK0
MEMORY
ARRAY
(16,384 x 1,024 x 16)
8
16
READ
LATCH
MUX
8
DQS
GENERATOR
COL0
8
CK
DATA
DLL
SENSE AMPLIFIERS
(16,384)
DRVRS
1
DQ0–
DQ7
INPUT
REGISTERS
1
MASK
1
1
1
2
8
16
8
8
8
8
RCVRS
DM
1
DQS
DQS
2
I/O GATING
DM MASK LOGIC
BANK
CONTROL
LOGIC
8
A0-A13,
BA0, BA1
16
ADDRESS
REGISTER
2
1024
16
WRITE
FIFO
&
DRIVERS
clk
out
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
10
clk
in DATA
11
CK
COL0
1
1
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
MICRON [ MICRON TECHNOLOGY ]
