PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM
8 Meg x 16
CKE
CK#
CK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
REFRESH
COUNTER
12
BANK1
COMMAND
DECODE
MODE REGISTERS
12
12
ROW-
ADDRESS
MUX
12
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 256 x 32)
16
32
READ
LATCH
MUX
16
DQS
GENERATOR
COL0
16
CK
DATA
DLL
SENSE AMPLIFIERS
8192
DRVRS
2
DQ0 -
DQ15,
LDM,
UDM
LDQS
UDQS
2
2
4
16
32
16
DATA
16
16
16
RCVRS
2
2
A0-A11,
BA0, BA1
ADDRESS
REGISTER
BANK
CONTROL
LOGIC
I/O GATING
DM MASK LOGIC
32
2
MASK
WRITE
FIFO
&
DRIVERS
ck
out
ck
in
INPUT
REGISTERS
2
DQS
14
2
256
(x32)
32
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
8
9
CK
COL0
2
1
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
