512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Tim in g Dia g ra m s
Tim in g Dia g ra m s
Fig u re 36: In it ia lize a n d Lo a d Mo d e Re g ist e r
Tn + 1
T0
T1
To + 1
Tp + 1
Tq + 1
Tr + 1
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
CLK
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
t
CK
t
t
CKS
CKH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
CKE
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
t
t
CMS CMH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
1
COMMAND
NOP
PRE
AR
AR
LMR
LMR
VALID
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
DQM
A0-A9, A11
A10
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
t
t
AS AH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
VALID
CODE
CODE
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
VALID
VALID
CODE
CODE
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
t
t
t
t
AS AH
AS AH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
BA0 = L,
BA1 = L
BBAA00 ==LL,,
BA0, BA1
DQ
( (
) )
( (
) )
( (
) )
( (
) )
BA1 = H
BA1 = L
( (
) )
( (
) )
( (
) )
High-Z
( (
((
))
((
))
((
))
((
))
((
))
((
))
)
)
T = 100µs
t
3
t
3
t
2
t
2
t
MRD
MRD
RFC
RFC
RP
Power-up:
DD and
CLK stable
Load Extended
Mode Register
Precharge
all banks
Load Mode
Register
V
DON’T CARE
Notes: 1. PRE = PRECHARGE command, AR = AUTO REFRESH command, LMR = LOAD MODE REGISTER
command.
t
2. Only NOPs or COMMAND INHIBITs may be issued during RFC time.
t
3. At least one NOP or COMMAND INHIBIT is required during MRD time.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
53
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