512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Re g ist e r De fin it io n
The mode registers must be loaded when all banks are idle, and the controller must wait
t
MRD before initiating the subsequent operation. Violating either of these requirements
will result in unspecified operation.
Bu rst Le n g t h (BL)
Read and write accesses to the SDRAM are burst oriented, with the BL being program-
mable, as shown in Figure 6 on page 14. The BL determines the maximum number of
column locations that can be accessed for a given READ or WRITE command. BL = 1, 2,
4, 8, or continuous locations are available for both the sequential and the interleaved
burst types, and a continuous-page burst is available for the sequential type. The contin-
uous-page burst is used in conjunction with the BURST TERMINATE command to
generate arbitrary BLs.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the BL is effec-
tively selected. All accesses for that burst take place within this block, meaning that the
burst will wrap within the block if a boundary is reached. The block is uniquely selected
by A1–A8 when BL = 2, A2–A8 when BL = 4, and A3–A8 when BL = 8. The remaining (least
significant) address bit(s) is (are) used to select the starting location within the block.
Bu rst Typ e
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the BL, the burst type, and the
starting column address, as shown in Table 4 on page 15.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
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