512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Co m m a n d s
Co m m a n d s
Table 5 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional Truth Tables appear on pages 41–44;
these tables provide current state/ next state information.
Ta b le 5:
Tru t h Ta b le – Co m m a n d s a n d DQM Op e ra t io n
Notes 4 and 5 apply to all commands
Na m e (Fu n ct io n )
CS# RAS# CAS# WE# DQM
ADDR
DQs
No t e s
H
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
X
X
X
X
X
1
COMMAND INHIBIT (NOP)
X
1
NO OPERATION (NOP)
X
Bank/Row
Bank/Col
2
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
H
H
H
L/H
L/H
X
3
3
L
Bank/Col Valid
H
L
X
X
6, 7, 8
BURST TERMINATE or deep power-down
(Enter deep power-down mode)
L
L
L
L
H
L
L
X
X
Code
X
X
X
9
PRECHARGE (Deactivate row in bank or banks)
H
10, 11
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
L
X
X
L
X
X
L
X
X
L
X
X
X
L
Op-Code
X
12
LOAD MODE REGISTER
X
X
Active
High-Z
Write enable/output enable
Write inhibit/output High-Z
H
Notes: 1. COMMAND INHIBIT and NOP are functionally interchangeable.
2. BA0–BA1 provide bank address and A0–A12 provide row address.
3. BA0–BA1 provide bank address; A0–A9 provide column address; A10 HIGH enables the auto
precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
4. CKE is HIGH for all commands shown except SELF REFRESH and deep power-down.
5. All states and sequences not shown are reserved and/or illegal.
6. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command
could coincide with data on the bus. However, the DQs column reads a don’t care state to
illustrate that the BURST TERMINATE command can occur when there is no data present.
7. Applies only to read and write bursts with auto precharge disabled; this command is unde-
fined and should not be used for READ bursts with auto precharge enabled.
8. This command is a BURST TERMINATE if CKE is HIGH, deep power-down if CKE is LOW.
9. A10 LOW: BA0–BA1 determine which bank is precharged. A10 HIGH: all banks are pre-
charged and BA0–BA1 are “Don’t Care.”
10. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
11. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
12. BA0–BA1 select either the standard mode register or the extended mode register (BA0 = 0,
BA1 = 0 select the standard mode register; BA0 = 0, BA1 = 1 select extended mode register;
other combinations of BA0–BA1 are reserved.) A0–A12 provide the op-code to be written to
the selected mode register.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
19
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