512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
No t e s
12. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
t
14. Timing actually specified by CKS; clock(s) specified as a reference only at minimum
cycle rate.
t
t
15. Timing actually specified by WR plus RP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by WR.
t
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
t
t
21. Based on CK = 7.5ns for -75, and CK = 8ns for -8, CL = 3.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = –2V for
a pulse width ≤ 3ns.
23. The only time that the clock frequency is allowed to change is during clock stop,
power down, or self-refresh modes.
t
24. Auto precharge mode only. The precharge timing budget ( RP) begins at 7ns for -8
after the first clock delay, after the last WRITE is executed. May not exceed limit set for
precharge mode.
25. Parameter guaranteed by design.
26. CKE is HIGH during refresh com mand period RFC (MIN), else CKE is LOW. The IDD7
t
limit is actually a nominal value and does not result in a fail value.
27. Values for IDD7 for 85°C are 100 percent tested. Values for 70°C, 45°C, and 15°C are
sampled only.
28. IOUT = 4mA for full-drive strength. Other drive strengths require appropriate scale.
29. Current is taken 500ms after entering into this operating mode to allow tester mea-
suring unit settling time.
30. Deep power-down current is a nominal value at 25°C. This parameter is not tested.
t
t
31. There must be one CK during the WR time for WRITE auto precharge.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
52
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