512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
General Description
Figure 1:
512Mb Mobile SDRAM Part Numbering
Power
Example Part Number: MT48H16M32LFCM-75IT:A
-
MT48
V
DD
/
V
DD
Q
Mobile
Configuration
Package
Speed
Temp. Revision
V
DD
/V
DD
Q
1.8V/1.8V
H
:A Design revision
Configuration Row Size Option
32 Meg x 16
16 Meg x 32
Standard
Standard
32M16LF
16M32LF
IT
Operating Temp.
Commercial
Industrial
16 Meg x 32 Reduced page-size 16M32LG
Power
Package
54-Ball (10 x 11.5 VFBGA) Pb–free
90-Ball (10 x 13 VFBGA) Pb–free
CJ
CM
L
Standard I
DD
2/I
DD
7
Low I
DD
2/I
DD
7
Speed Grade
-75
-8
t
CK
t
CK
= 7.5ns
= 8.0ns
General Description
The Micron
®
512Mb Mobile SDRAM is a high-speed CMOS, dynamic random-access
memory containing 536,870,912-bits. It is internally configured as a quad-bank DRAM
with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1K
columns by 16 bits. Each of the x32’s 134,217,728-bit banks is organized as 8,192 rows by
512 columns by 32 bits. In a reduced page-size option, each of the x32’s 134,217,728-bit
banks is organized as 16,384 rows by 256 columns x32 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A12 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations with a read burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed oper-
ation. This architecture is compatible with the 2n rule of prefetch architectures, but it
also allows the column address to be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank while accessing one of the other three
banks will hide the PRECHARGE cycles and provide seamless high-speed, random-
access operation.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
