512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Tim in g Dia g ra m s
Fig u re 50: Sin g le WRITE – Wit h o u t Au t o Pre ch a rg e
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
3
3
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
t
CMH
CMS
DQM
t
t
AH
AS
ROW
COLUMN
m
ADDR
t
t
t
AH
AS
AS
ALL BANKS
ROW
ROW
A10
SINGLE BANK
BANK
DISABLE AUTO PRECHARGE
BANK
t
AH
BA0, BA1
BANK
BANK
t
t
DH
DS
DIN m
DQ
t
t
2
WR
t
RP
RCD
t
t
RAS
RC
DON’T CARE
Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a manual PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
t
3. PRECHARGE command not allowed or RAS would be violated.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
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