512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 21 on page 32, or each subsequent WRITE may be
performed to a different bank.
Figure 19:
WRITE Burst
T0
CLK
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL
n
DQ
D
IN
n
D
IN
n
+1
DON’T CARE
Notes:
1. BL = 2. DQM is LOW.
Figure 20:
WRITE-to-WRITE
T0
CLK
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL
n
BANK,
COL
b
DQ
D
IN
n
D
IN
n
+1
D
IN
b
DON’T CARE
Notes:
1. DQM is LOW. Each WRITE command may be to any bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
Once the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 22 on page 32. Data
n
+ 1 is either the
last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not acti-
vated). The PRECHARGE command should be issued
t
WR after the clock edge at which
the last desired input data element is registered. The auto precharge mode requires a
t
WR of at least one clock plus time, regardless of frequency.
In addition, when truncating a WRITE burst at high clock frequencies (
t
CK < 15ns), the
DQM signal must be used to mask input data for the clock edge prior to, and the clock
edge coincident with, the PRECHARGE command. An example is shown in Figure 23 on
n
+ 1 is either the last of a burst of two or the last desired of a longer burst.
Following the PRECHARGE command, a subsequent command to the same bank
cannot be issued until
t
RP is met.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
31
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©2005 Micron Technology, Inc. All rights reserved.
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